參數(shù)資料
型號： DSP56600
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
中文描述： 維特比解碼器實現(xiàn)上使用DSP的家庭教學(xué)的VSL
文件頁數(shù)： 55/108頁
文件大?。?/td> 726K
代理商： DSP56600
Algorithmic Extensions
Allowing More General Branch Metrics
Viterbi Decoder Implementation
For More Information On This Product,
Go to: www.freescale.com
4-7
For this example, we are using the same code as in
Section 3
to make the unnormalized
branch metrics symmetrical. For easy storage in memory, we want to generate metric
pairs. Each pair should have the values needed for the upper and lower branch metric
value needed for the butterfly. For this example, the branch metric for encoder output 00
will be paired with the branch metric value for 11 and the value for 01 paired with the
value for 10. All branch metrics will have the previous path metric for state 0 subtracted
from them. This means that after the Viterbi butterfly update, each path metric value
will have been normalized. It can be shown that this limits the worst case path metric
values to be no more than 12 times the maximum branch metric value (for this code
example).
The branch metric macro begins by reading in the last path metric for state 0. It then
negates that value in accumulator a and reads the decoder input into register y. The data
in y is assumed to be in the form y1:y0 mapped to real:imaginary data input. Next, the
scaling factor -16 is placed in register x1.
The mac instruction finds a partial branch metric by multiplying the real data by the
scaling factor and adding the result to the negated path metric value in a. We also save
the negated path metric value to b for later use.
Next, we move the real decoder input from y1 to x0. The next mac instruction multiplies
imaginary input by the scaling factor and adds it to a. The accumulator a now has the
normalized branch metric for encoder 00 outputs. At the same time, the partial branch
metric that was in a is saved in y1 for later use.
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
endm
x,l:(r2)+
ab,l:(r2)+
ba,l:(r2)+
y,l:(r2)+
y,l:(r2)+
ba,l:(r2)+
ab,l:(r2)+
x,l:(r2)+
ba,l:(r2)+
y,l:(r2)+
x,l:(r2)+
ab,l:(r2)+
ab,l:(r2)+
x,l:(r2)+
y,l:(r2)+
ba,l:(r2)+
;store 11 in location 0.
;store 01 in location 1
;store 10 in location 2
;store 00 in location 3
;store 00 in location 4
;store 10 in location 5
;store 01 in location 6
;store 11 in location 7
;store 10 in location 8
;store 00 in location 9
;store 11 in location 10
;store 01 in location 11
;store 01 in location 12
;store 11 in location 13
;store 00 in location 14
;store 10 in location 15 r2-> BRX
Example 4-2
Modified Branch Metric Generation Code (Continued)
F
Freescale Semiconductor, Inc.
n
.
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