參數(shù)資料
型號(hào)： DSP56366P
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 8/110頁(yè)
文件大?。?/td> 1273K
代理商： DSP56366P
DSP56366 Technical Data, Rev. 3.1
2-4
Freescale Semiconductor
2.4
Clock and PLL
2.5
External Memory Expansion Port (Port A)
When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and
tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.
GND
D
(4)
Data Bus Ground
—GND
D
is an isolated ground for sections of the data bus I/O drivers. This connection
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are four GND
D
connections.
GND
C
(2)
Bus Control Ground
—GND
C
is an isolated ground for the bus control I/O drivers. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GND
C
connections.
GND
H
Host Ground
—GND
h
is an isolated ground for the HD08 I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There is one GND
H
connection.
GND
S
(2)
SHI, ESAI, ESAI_1, DAX and Timer Ground
—GND
S
is an isolated ground for the SHI, ESAI, ESAI_1,
DAX and Timer. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There are two GND
S
connections.
Table 2-4 Clock and PLL Signals
Signal
Name
Type
State
during
Reset
Signal Description
EXTAL
Input
Input
External Clock Input
—An external clock source must be connected to EXTAL in order
to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5 V
.
PCAP
Input
Input
PLL Capacitor
—PCAP is an input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
CCP
.
If the PLL is not used, PCAP may be tied to V
CC
, GND, or left floating.
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt
—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion and
during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized
to internal system clock.
This input cannot tolerate 5 V
.
Table 2-3 Grounds (continued)
Ground Name
Description
相關(guān)PDF資料
PDF描述
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
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