參數(shù)資料
型號(hào)： DSP56366P
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁數(shù)： 64/110頁
文件大?。?/td> 1273K
代理商： DSP56366P
DSP56366 Technical Data, Rev. 3.1
3-38
Freescale Semiconductor
333
HCS hold time after data strobe deassertion
9
—
0.0
—
ns
334
Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)
—
4.7
—
ns
335
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
—
3.3
—
ns
336
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
strobe assertion
9
Read
Write
—
0
4.7
—
—
ns
337
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
deassertion
9
—
3.3
—
ns
338
Delay from read data strobe deassertion to host request assertion for “Last
Data Register” read
4
,
5
,
10
T
C
8.3
—
ns
339
Delay from write data strobe deassertion to host request assertion for “Last
Data Register” write
5
,
8
,
10
2
×
T
C
16.7
—
ns
340
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD = 0)
5
,
9
,
10
—
—
19.1
ns
341
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD = 1, open drain Host Request)
5
,
9
,
10
,
11
—
—
300.0
ns
342
Delay from DMA HACK deassertion to HOREQ assertion
For “Last Data Register” read
5
For “Last Data Register” write
5
For other cases
2
×
T
C
+ 19.1
1.5
×
T
C
+ 19.1
35.8
31.6
0.0
—
—
—
ns
343
Delay from DMA HACK assertion to HOREQ deassertion
HROD = 0
5
—
—
20.2
ns
344
Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
HROD = 1, open drain Host Request
5
,
11
—
—
300.0
ns
1
See Host Port Usage Considerations in the DSP56366 User’s Manual.
2
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3
V
CC
= 3.3 V
±
0.16 V; T
J
=
–40°C to +110°C, C
L
= 50 pF
4
The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
5
The “l(fā)ast data register” is the register at address $7, which is the last location to be read or written in data transfers.
6
This timing is applicable only if a read from the “l(fā)ast data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
7
This timing is applicable only if two consecutive reads from one of these registers are executed.
8
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9
The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single
data strobe mode.
10
The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.
11
In this calculation, the host request signal is pulled up by a 4.7 k
Ω
resistor in the open-drain mode.
Table 3-18 Host Interface (HDI08) Timing
1, 2
(continued)
No.
Characteristics
3
Expression
120 MHz
Unit
Min
Max
相關(guān)PDF資料
PDF描述
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*