參數(shù)資料
型號(hào): DSP56366P
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 78/110頁(yè)
文件大?。?/td> 1273K
代理商: DSP56366P
DSP56366 Technical Data, Rev. 3.1
3-52
Freescale Semiconductor
3.13.1
Programming the Serial Clock
The programmed serial clock cycle, T
I
HCKR (SHI clock control register).
2
CCP
, is specified by the value of the HDM[7:0] and HRS bits of the
The expression for T
I
2
CCP
is
where
HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight
prescaler is operational. When HRS is set, the prescaler is bypassed.
HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256
(HDM[7:0] = $00 to $FF) may be selected.
In I
2
C mode, the user may select a value for the programmed serial clock cycle from
to
The programmed serial clock cycle (T
I
in order to achieve the desired SCL serial clock cycle (T
SCL
), as shown in
Table 3-21
.
Table 3-21 SCL Serial Clock Cycle (T
SCL
) generated as Master
2
CCP
), SCL rise time (T
R
), and the filters selected should be chosen
EXAMPLE:
For DSP clock frequency of 120 MHz (i.e. T
C
= 8.33ns), operating in a standard mode I
2
C environment
(F
SCL
= 100 kHz (i.e. T
SCL
= 10
μ
s), T
R
= 1000ns), with wide filters enabled:
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $41 (=65).
Filters bypassed
T
I
2
CCP
+ 2.5
×
T
C
+ 45ns +
T
R
Narrow filters enabled
T
I
2
CCP
+ 2.5
×
T
C
+ 135ns +
T
R
Wide filters enabled
T
I
2
CCP
+ 2.5
×
T
C
+ 223ns +
T
R
T
I
2
CCP
T
[
C
2
×
HDM 7
:
0
]
(
1
)
7
1
HRS
(
)
1
+
×
(
)
×
+
×
]
=
6
T
C
if
×
HDM 7
:
0
]
02
and
HRS
$
1
=
=
4096
T
C
if
×
HDM 7
:
0
]
FF
and
HRS
$
0
=
=
T
I
2
CCP
10
μ
s
2.5
8.33ns
×
223ns
1000ns
8756ns
=
=
HDM 7
:
0
]
8756ns
2
(
8.33ns
×
8
)
1
64.67
=
×
=
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