參數(shù)資料
型號(hào)： DSP56366P
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 53/110頁(yè)
文件大?。?/td> 1273K
代理商： DSP56366P
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor
3-27
191
RD assertion to RAS deassertion
t
ROH
4.5
×
T
C
4.0
221.0
—
146.0
—
ns
192
RD assertion to data valid
t
GA
4
×
T
C
7.5
—
192.5
—
125.8
ns
193
RD deassertion to data not valid
3
t
GZ
0.0
—
0.0
—
ns
194
WR assertion to data active
0.75
×
T
C
0.3
37.2
—
24.7
—
ns
195
WR deassertion to data high impedance
0.25
×
T
C
—
12.5
—
8.3
ns
1
The number of wait states for out of page access is specified in the DCR.
2
The refresh period is specified in the DCR.
3
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ
.
4
Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See
Figure 3-17
.).
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
1, 2
No.
Characteristics
3
Symbol
Expression
4
66 MHz
80 MHz
Unit
Min
Max
Min
Max
157 Random read or write cycle time
t
RC
9
×
T
C
136.4
—
112.5
—
ns
158 RAS assertion to data valid (read)
t
RAC
4.75
×
T
C
7.5
4.75
×
T
C
6.5
—
—
64.5
—
—
—
—
52.9
ns
159 CAS assertion to data valid (read)
t
CAC
2.25
×
T
C
7.5
2.25
×
T
C
6.5
—
—
26.6
—
—
—
—
21.6
ns
160 Column address valid to data valid (read)
t
AA
3
×
T
C
7.5
3
×
T
C
6.5
—
—
40.0
—
—
—
—
31.0
ns
161 CAS deassertion to data not valid (read hold
time)
t
OFF
0.0
—
0.0
—
ns
162 RAS deassertion to RAS assertion
t
RP
3.25
×
T
C
4.0
45.2
—
36.6
—
ns
163 RAS assertion pulse width
t
RAS
5.75
×
T
C
4.0
83.1
—
67.9
—
ns
164 CAS assertion to RAS deassertion
t
RSH
3.25
×
T
C
4.0
45.2
—
36.6
—
ns
165 RAS assertion to CAS deassertion
t
CSH
4.75
×
T
C
4.0
68.0
—
55.5
—
ns
166 CAS assertion pulse width
t
CAS
2.25
×
T
C
4.0
30.1
—
24.1
—
ns
167 RAS assertion to CAS assertion
t
RCD
2.5
×
T
C
±
2
35.9
39.9
29.3
33.3
ns
168 RAS assertion to column address valid
t
RAD
1.75
×
T
C
±
2
24.5
28.5
19.9
23.9
ns
Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
1, 2
(continued)
No.
Characteristics
3
Symbol
Expression
20 MHz
4
30 MHz
4
Unit
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
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