參數(shù)資料
型號(hào)： DSP56366P
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 30/110頁(yè)
文件大?。?/td> 1273K
代理商： DSP56366P
DSP56366 Technical Data, Rev. 3.1
3-4
Freescale Semiconductor
3.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
IL
maximum
of 0.3 V and a V
IH
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels
shown in Note 3 of the previous table. AC timing specifications, which are referenced to a device input
signal, are measured in production with respect to the 50% point of the respective input signal’s transition.
DSP56366 output levels are measured with the production test machine V
OL
and V
OH
reference levels set
at 0.4 V and 2.4 V, respectively.
NOTE
Although the minimum value for the frequency of EXTAL is 0 MHz, the
device AC test conditions are 15 MHz and rated speed.
3.6
Internal Clocks
6
Appendix A, "Power Consumption Benchmark"
provides a formula to compute the estimated current requirements
in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are
based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the
measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with
V
CC
= 3.3 V at
T
J
= 110°C. Maximum internal supply current is measured with V
CC
= 3.46 V at T
J
= 110°C.
7
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to
float).
Table 3-4 Internal Clocks
Characteristics
Symbol
Expression
1, 2
Min
Typ
Max
Internal operation frequency with PLL
enabled
f
—
(Ef
×
MF)/(PDF
×
DF)
—
Internal operation frequency with PLL
disabled
f
—
Ef/2
—
Internal clock high period
With PLL disabled
With PLL enabled and MF
≤
4
With PLL enabled and MF > 4
T
H
—
0.49
×
ET
C
×
PDF
×
DF/MF
0.47
×
ET
C
×
PDF
×
DF/MF
ET
C
—
—
—
0.51
×
ET
C
×
PDF
×
DF/MF
0.53
×
ET
C
×
PDF
×
DF/MF
Internal clock low period
With PLL disabled
With PLL enabled and MF
≤
4
With PLL enabled and MF > 4
T
L
—
0.49
×
ET
C
×
PDF
×
DF/MF
0.47
×
ET
C
×
PDF
×
DF/MF
ET
C
—
—
—
0.51
×
ET
C
×
PDF
×
DF/MF
0.53
×
ET
C
×
PDF
×
DF/MF
Internal clock cycle time with PLL
enabled
T
C
—
ET
C
×
PDF
×
DF/MF
—
相關(guān)PDF資料
PDF描述
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
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