參數(shù)資料
型號(hào)： DSP56366P
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 44/110頁(yè)
文件大?。?/td> 1273K
代理商： DSP56366P
DSP56366 Technical Data, Rev. 3.1
3-18
Freescale Semiconductor
150
CAS assertion to data not valid (write)
t
DH
0.75
×
T
C
4.0
33.5
—
21.0
—
ns
151
WR assertion to CAS assertion
t
WCS
T
C
4.3
45.7
—
29.0
—
ns
152
Last RD assertion to RAS deassertion
t
ROH
1.5
×
T
C
4.0
71.0
—
46.0
—
ns
153
RD assertion to data valid
t
GA
T
C
7.5
—
42.5
—
25.8
ns
154
RD deassertion to data not valid
6
t
GZ
0.0
—
0.0
—
ns
155
WR assertion to data active
0.75
×
T
C
0.3
37.2
—
24.7
—
ns
156
WR deassertion to data high impedance
0.25
×
T
C
—
12.5
—
8.3
ns
1
The number of wait states for Page mode access is specified in the DCR.
2
The refresh period is specified in the DCR.
3
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
PC
equals 2
×
T
C
for
read-after-read or write-after-write sequences).
4
Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See
Figure 3-14
.).
5
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
6
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ
.
Table 3-10 DRAM Page Mode Timings, Two Wait States
1, 2, 3, 4
No.
Characteristics
Symbol
Expression
5
66 MHz
80 MHz
Unit
Min
Max
Min
Max
131
Page mode cycle time for two consecutive
accesses of the same direction
Page mode cycle time for mixed (read and write)
accesses
t
PC
2
×
T
C
1.25
×
T
C
45.4
41.1
—
—
37.5
34.4
—
—
ns
132
CAS assertion to data valid (read)
t
CAC
1.5
×
T
C
7.5
1.5
×
T
C
6.5
—
—
15.2
—
—
—
—
12.3
ns
ns
133
Column address valid to data valid (read)
t
AA
2.5
×
T
C
7.5
2.5
×
T
C
6.5
—
—
30.4
—
—
—
—
24.8
ns
ns
134
CAS deassertion to data not valid (read hold
time)
t
OFF
0.0
—
0.0
—
ns
135
Last CAS assertion to RAS deassertion
t
RSH
1.75
×
T
C
4.0
22.5
—
17.9
—
ns
136
Previous CAS deassertion to RAS deassertion
t
RHCP
3.25
×
T
C
4.0
45.2
—
36.6
—
ns
137
CAS assertion pulse width
t
CAS
1.5
×
T
C
4.0
18.7
—
14.8
—
ns
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)
1, 2, 3
(continued)
No.
Characteristics
Symbol
Expression
20 MHz
4
30 MHz
4
Unit
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
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