參數(shù)資料
型號: DSP56366P
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 24位音頻數(shù)字信號處理器
文件頁數(shù): 43/110頁
文件大小: 1273K
代理商: DSP56366P
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor
3-17
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)
1, 2, 3
No.
Characteristics
Symbol
Expression
20 MHz
4
30 MHz
4
Unit
Min
Max
Min
Max
131
Page mode cycle time for two consecutive
accesses of the same direction
Page mode cycle time for mixed (read and
write) accesses
t
PC
2
×
T
C
1.25
×
T
C
100.0
62.5
66.7
41.7
ns
132
CAS assertion to data valid (read)
t
CAC
T
C
7.5
42.5
25.8
ns
133
Column address valid to data valid (read)
t
AA
1.5
×
T
C
7.5
67.5
42.5
ns
134
CAS deassertion to data not valid (read hold
time)
t
OFF
0.0
0.0
ns
135
Last CAS assertion to RAS deassertion
t
RSH
0.75
×
T
C
4.0
33.5
21.0
ns
136
Previous CAS deassertion to RAS
deassertion
t
RHCP
2
×
T
C
4.0
96.0
62.7
ns
137
CAS assertion pulse width
t
CAS
0.75
×
T
C
4.0
33.5
21.0
ns
138
Last CAS deassertion to RAS deassertion
5
BRW[1:0] = 00
BRW[1:0] = 01
BRW[1:0] = 10
BRW[1:0] = 11
t
CRP
1.75
×
T
C
6.0
3.25
×
T
C
6.0
4.25
×
T
C
6.0
6.25
×
T
C
– 6.0
81.5
156.5
206.5
306.5
52.3
102.2
135.5
202.1
ns
139
CAS deassertion pulse width
t
CP
0.5
×
T
C
4.0
21.0
12.7
ns
140
Column address valid to CAS assertion
t
ASC
0.5
×
T
C
4.0
21.0
12.7
ns
141
CAS assertion to column address not valid
t
CAH
0.75
×
T
C
4.0
33.5
21.0
ns
142
Last column address valid to RAS
deassertion
t
RAL
2
×
T
C
4.0
96.0
62.7
ns
143
WR deassertion to CAS assertion
t
RCS
0.75
×
T
C
3.8
33.7
21.2
ns
144
CAS deassertion to WR assertion
t
RCH
0.25
×
T
C
3.7
8.8
4.6
ns
145
CAS assertion to WR deassertion
t
WCH
0.5
×
T
C
4.2
20.8
12.5
ns
146
WR assertion pulse widt
h
t
WP
1.5
×
T
C
4.5
70.5
45.5
ns
147
Last WR assertion to RAS deassertion
t
RWL
1.75
×
T
C
4.3
83.2
54.0
ns
148
WR assertion to CAS deassertion
t
CWL
1.75
×
T
C
4.3
83.2
54.0
ns
149
Data valid to CAS assertion (Write)
t
DS
0.25
×
T
C
4.0
8.5
4.3
ns
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