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參數(shù)資料
| 型號(hào)： | DSP56364P |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 8/148頁(yè) |
| 文件大?。?/td> | 1204K |
| 代理商： | DSP56364P |
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Clock and PLL
DSP56364 Technical Data, Rev. 4
2-4
Freescale Semiconductor
2.4
Clock and PLL
2.5
External Memory Expansion Port (Port A)
When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant port A
signals: D0–D7, AA0, AA1, RD, WR, CAS.
2.5.1
External Address Bus
GND
C
(1)
Bus Control Ground
—GND
C
is an isolated ground for the bus control I/O drivers. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There is one GND
C
connections.
GND
S
(3)
SHI and ESAI
—GND
S
is an isolated ground for the SHI and ESAI. This connection must be tied externally
to all other chip ground connections. The user must provide adequate external decoupling capacitors.
There are three GND
S
connections.
Table 2-4 Clock and PLL Signals
Signal Name
Type
State during
Reset
Signal Description
EXTAL
Input
Input
External Clock Input
—An external clock source must be connected to EXTAL in
order to supply the clock to the internal clock generator and PLL.
PCAP
Input
Input
PLL Capacitor
—PCAP is an input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
CCP
.
If the PLL is not used, PCAP may be tied to V
CC
, GND, or left floating.
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt
—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion and
during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
This input is 5 V tolerant
.
Table 2-5 External Address Bus Signals
Signal Name
Type
State during
Reset
Signal Description
A0–A17
Output
Keeper active
Address Bus
—A0–A17 are active-high outputs that specify the address for
external program and data memory accesses. Otherwise, the signals are kept
to their previous values by internal weak keepers. To minimize power
dissipation, A0–A17 do not change state when external memory spaces are not
being accessed.
Table 2-3 Grounds (continued)
Ground Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56366P | 24-Bit Audio Digital Signal Processor |
| DSP56366UM | 24-Bit Audio Digital Signal Processor |
| DSP56367P | 24-Bit Audio Digital Signal Processor |
| DSP56367UM | 24-Bit Audio Digital Signal Processor |
| DSP56600 | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56364UM | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual |
| DSP56366 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor |
| DSP56366P | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56366UM | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56367 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Optoelectronic |
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