參數(shù)資料
型號： DSP56364P
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號處理器
文件頁數(shù)： 49/148頁
文件大小： 1204K
代理商： DSP56364P
External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
3-33
191
RD assertion to RAS deassertion
t
ROH
11.5
×
T
C
4.0
111.0
—
ns
192
RD assertion to data valid
t
GA
10
×
T
C
7.0
—
93.0
ns
193
RD deassertion to data not valid
3
t
GZ
0.0
—
ns
194
WR assertion to data active
0.75
×
T
C
0.3
7.2
—
ns
195
WR deassertion to data high impedance
0.25
×
T
C
—
2.5
ns
1
The number of wait states for out-of-page access is specified in the DCR.
2
The refresh period is specified in the DCR.
3
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ
.
4
The asynchronous delays specified in the expressions are valid for DSP56364.
5
Either t
RCH
or t
RRH
must be satisfied for read cycles.
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
1, 2
No.
Characteristics
3
Symbol
Expression
Min
Max
Unit
157
Random read or write cycle time
t
RC
16
×
T
C
160.0
—
ns
158
RAS assertion to data valid (read)
t
RAC
8.25
×
T
C
5.7
—
76.8
ns
159
CAS assertion to data valid (read)
t
CAC
4.75
×
T
C
5.7
—
41.8
ns
160
Column address valid to data valid (read)
t
AA
5.5
×
T
C
5.7
—
49.3
ns
161
CAS deassertion to data not valid (read hold time)
t
OFF
0.0
0.0
—
ns
162
RAS deassertion to RAS assertion
t
RP
6.25
×
T
C
4.0
58.5
—
ns
163
RAS assertion pulse width
t
RAS
9.75
×
T
C
4.0
93.5
—
ns
164
CAS assertion to RAS deassertion
t
RSH
6.25
×
T
C
4.0
58.5
—
ns
165
RAS assertion to CAS deassertion
t
CSH
8.25
×
T
C
4.0
78.5
—
ns
166
CAS assertion pulse width
t
CAS
4.75
×
T
C
4.0
43.5
—
ns
167
RAS assertion to CAS assertion
t
RCD
3.5
×
T
C
±
2
33.0
37.0
ns
168
RAS assertion to column address valid
t
RAD
2.75
×
T
C
±
2
25.5
29.5
ns
169
CAS deassertion to RAS assertion
t
CRP
7.75
×
T
C
4.0
73.5
—
ns
170
CAS deassertion pulse width
t
CP
6.25
×
T
C
4.0
58.5
—
ns
171
Row address valid to RAS assertion
t
ASR
6.25
×
T
C
4.0
58.5
—
ns
172
RAS assertion to row address not valid
t
RAH
2.75
×
T
C
4.0
23.5
—
ns
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
1, 2
(continued)
No.
Characteristics
3
Symbol
Expression
4
Min
Max
Unit
相關(guān)PDF資料
PDF描述
DSP56366P 24-Bit Audio Digital Signal Processor
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56364UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual
DSP56366 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor
DSP56366P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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