參數(shù)資料
型號(hào)： DSP56364P
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁數(shù)： 20/148頁
文件大?。?/td> 1204K
代理商： DSP56364P
AC Electrical Characteristics
DSP56364 Technical Data, Rev. 4
3-4
Freescale Semiconductor
3.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V
IL
maximum
of 0.3 V and a V
IH
minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels
shown in
Note
8
of the previous table. AC timing specifications, which are referenced to a device input
signal, are measured in production with respect to the 50% point of the respective input signal’s transition.
DSP56364 output levels are measured with the production test machine V
OL
and V
OH
reference levels set
at 0.4 V and 2.4 V, respectively.
NOTE
Although the minimum value for the frequency of EXTAL is 0 MHz, the
device AC test conditions are 15 MHz and rated speed.
3.6
Internal Clocks
5
This characteristic does not apply to PCAP.
6
Section 5, "Design Considerations"
provides a formula to compute the estimated current requirements in Normal
mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on
synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results
of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V
CC
= 3.3 V at T
J
= 105°C. Maximum internal supply current is measured with V
CC
= 3.46 V at T
J
= 105°C.
7
In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is disabled during Stop
state.
8
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to
float).
Table 3-4 Internal Clocks
Characteristics
Symbol
Expression
1, 2
Min
Typ
Max
Internal operation frequency with PLL enabled
f
—
(Ef
×
MF)/
(PDF
×
DF)
—
Internal operation frequency with PLL disabled
f
—
Ef/2
—
Internal clock high period
T
H
With PLL disabled
—
ET
C
—
With PLL enabled and MF
≤
4
0.49
×
ET
C
×
PDF
×
DF/MF
—
0.51
×
ET
C
×
PDF
×
DF/MF
With PLL enabled and MF > 4
0.47
×
ET
C
×
PDF
×
DF/MF
—
0.53
×
ET
C
×
PDF
×
DF/MF
相關(guān)PDF資料
PDF描述
DSP56366P 24-Bit Audio Digital Signal Processor
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56364UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual
DSP56366 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor
DSP56366P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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