參數(shù)資料
型號: DSP56364P
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 24位音頻數(shù)字信號處理器
文件頁數(shù): 43/148頁
文件大小: 1204K
代理商: DSP56364P
External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
3-27
Figure 3-14 DRAM Out-of-Page Wait States Selection Guide
Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States
1, 2
No.
Characteristics
3
Symbol
Expression
20 MHz
4
30 MHz
4
Unit
Min
Max
Min
Max
157
Random read or write cycle time
t
RC
5
×
T
C
250.0
166.7
ns
158
RAS assertion to data valid (read)
t
RAC
2.75
×
T
C
7.5
130.0
84.2
ns
159
CAS assertion to data valid (read)
t
CAC
1.25
×
T
C
7.5
55.0
34.2
ns
160
Column address valid to data valid
(read)
t
AA
1.5
×
T
C
7.5
67.5
42.5
ns
161
CAS deassertion to data not valid
(read hold time)
t
OFF
0.0
0.0
ns
162
RAS deassertion to RAS assertion
t
RP
1.75
×
T
C
4.0
83.5
54.3
ns
163
RAS assertion pulse width
t
RAS
3.25
×
T
C
4.0
158.5
104.3
ns
164
CAS assertion to RAS deassertion
t
RSH
1.75
×
T
C
4.0
83.5
54.3
ns
Chip Frequency
(MHz)
DRAM Type
(tRAC ns)
100
80
70
50
66
80
100
4 Wait States
8 Wait States
11 Wait States
15 Wait States
Note: This figure should be use for primary selection. For exact and
detailed timings see the following tables.
60
40
120
AA0475
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