參數(shù)資料
型號： DSP56364P
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號處理器
文件頁數(shù)： 12/148頁
文件大小： 1204K
代理商： DSP56364P
Serial Host Interface
DSP56364 Technical Data, Rev. 4
2-8
Freescale Semiconductor
HA0
Input
Tri-stated
I
2
C Slave Address 0
—This signal uses a Schmitt-trigger input when configured for the
I
2
C mode. When configured for I
2
C slave mode, the HA0 signal is used to form the
slave device address. HA0 is ignored when configured for the I
2
C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
SS
Input
Input
SPI Slave Select
—This signal is an active low Schmitt-trigger input when configured
for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable
the SPI slave for transfer. When configured for the SPI master mode, this signal should
be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus
error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance state.
HA2
Input
Input
I
2
C Slave Address 2
—This signal uses a Schmitt-trigger input when configured for the
I
2
C mode. When configured for the I
2
C Slave mode, the HA2 signal is used to form the
slave device address. HA2 is ignored in the I
2
C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant
.
HREQ
Input or
Output
Tri-stated
Host Request
—This signal is an active low Schmitt-trigger input when configured for
the master mode but an active low output when configured for the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready
for the next data word transfer and deasserted at the first clock pulse of the new data
word transfer. When configured for the master mode, HREQ is an input. When asserted
by the external slave device, it will trigger the start of the data word transfer by the
master. After finishing the data word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in
this state.
This input is 5 V tole
rant.
Table 2-9 Serial Host Interface Signals (continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
相關(guān)PDF資料
PDF描述
DSP56366P 24-Bit Audio Digital Signal Processor
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56364UM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual
DSP56366 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor
DSP56366P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
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