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參數(shù)資料
| 型號： | DSP56364P |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 11/148頁 |
| 文件大?。?/td> | 1204K |
| 代理商： | DSP56364P |
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Serial Host Interface
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
2-7
2.7
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I
2
C mode.
Serial Host Interface
Table 2-9 Serial Host Interface Signals
Signal
Name
Signal
Type
State during
Reset
Signal Description
SCK
Input or
output
Tri-stated
SPI Serial Clock
—The SCK signal is an output when the SPI is configured as a master
and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is
configured as a master, the SCK signal is derived from the internal SHI clock generator.
When the SPI is configured as a slave, the SCK signal is an input, and the clock signal
from the external master synchronizes the data transfer. The SCK signal is ignored by
the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both
the master and slave SPI devices, data is shifted on one edge of the SCK signal and is
sampled on the opposite edge where data is stable. Edge polarity is determined by the
SPI transfer protocol.
SCL
Input or
output
Tri-stated
I
2
C Serial Clock
—SCL carries the clock for I
2
C bus transactions in the I
2
C mode. SCL
is a Schmitt-trigger input when configured as a slave and an open-drain output when
configured as a master. SCL should be connected to V
CC
through a pull-up resistor.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
MISO
Input or
output
Tri-stated
SPI Master-In-Slave-Out
—When the SPI is configured as a master, MISO is the
master data input line. The MISO signal is used in conjunction with the MOSI signal for
transmitting and receiving serial data. This signal is a Schmitt-trigger input when
configured for the SPI Master mode, an output when configured for the SPI Slave
mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An
external pull-up resistor is not required for SPI operation.
SDA
Input or
open-drain
output
Tri-stated
I
2
C Data and Acknowledge
—In I
2
C mode, SDA is a Schmitt-trigger input when
receiving and an open-drain output when transmitting. SDA should be connected to
V
CC
through a pull-up resistor. SDA carries the data for I
2
C transactions. The data in
SDA must be stable during the high period of SCL. The data in SDA is only allowed to
change when SCL is low. When the bus is free, SDA is high. The SDA line is only
allowed to change during the time SCL is high in the case of start and stop events. A
high-to-low transition of the SDA line while SCL is high is a unique situation, and is
defined as the start event. A low-to-high transition of SDA while SCL is high is a unique
situation defined as the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
MOSI
Input or
output
Tri-stated
SPI Master-Out-Slave-In
—When the SPI is configured as a master, MOSI is the
master data output line. The MOSI signal is used in conjunction with the MISO signal
for transmitting and receiving serial data. MOSI is the slave data input line when the
SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for
the SPI Slave mode.
相關(guān)PDF資料 |
PDF描述 |
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| DSP56366P | 24-Bit Audio Digital Signal Processor |
| DSP56366UM | 24-Bit Audio Digital Signal Processor |
| DSP56367P | 24-Bit Audio Digital Signal Processor |
| DSP56367UM | 24-Bit Audio Digital Signal Processor |
| DSP56600 | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56364UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual |
| DSP56366 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor |
| DSP56366P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56366UM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56367 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
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