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| 型號： | DSP56364P |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 25/148頁 |
| 文件大小： | 1204K |
| 代理商： | DSP56364P |
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Reset, Stop, Mode Select, and Interrupt Timing
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
3-9
29
Delay from
IRQA
,
IRQB
,
IRQD
,
NMI
assertion to external
memory (DMA source) access address out valid
4.25
×
T
C
+ 2.0
44.0
—
ns
1
V
CC
= 3.3 V ± 0.16 V; T
J
= 0°C to + 105°C, C
L
= 50 pF
2
Use expression to compute maximum value.
3
Periodically sampled and not 100% tested
4
For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
CC
is valid, and
the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and V
CC
is valid. The specified
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the
crystal and other components connected to the oscillator and reflects worst case conditions.
When the V
CC
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
5
For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
CC
is valid, and
the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and V
CC
is valid. The specified
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the
crystal and other components connected to the oscillator and reflects worst case conditions.
When the V
CC
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
6
When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent
multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
7
WS = number of wait states (measured in clock cycles, number of T
C
)
8
This timing depends on several settings:
For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL
Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting
the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended
and these specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by
the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay
counter completes count or PLL lock procedure completion.
PLC value for PLL disable is 0.
The maximum value for ET
C
is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100
MHz = 40
μ
s). During the stabilization period, T
C
, T
H,
and T
L
will not be constant, and their width may vary, so timing may vary
as well.
9. If PLL does not lose lock.
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
1
(continued)
No.
Characteristics
Expression
2
Min
Max
Unit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56366P | 24-Bit Audio Digital Signal Processor |
| DSP56366UM | 24-Bit Audio Digital Signal Processor |
| DSP56367P | 24-Bit Audio Digital Signal Processor |
| DSP56367UM | 24-Bit Audio Digital Signal Processor |
| DSP56600 | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56364UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56364 24-Bit Digital Signal Processor User＇s Manual |
| DSP56366 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56366 24-Bit Audio Digital Signal Processor |
| DSP56366P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56366UM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56367 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
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