參數(shù)資料
型號(hào): DSP56364P
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 24位音頻數(shù)字信號(hào)處理器
文件頁數(shù): 55/148頁
文件大?。?/td> 1204K
代理商: DSP56364P
Serial Host Interface SPI Protocol Timing
DSP56364 Technical Data, Rev. 4
Freescale Semiconductor
3-39
152
SCK edge to data out valid
(data out delay time)
Master/
Slave
Bypassed
2
×
T
C
+33
53
ns
Narrow
2
×
T
C
+123
143
ns
Wide
2
×
T
C
+210
230
ns
153
SCK edge to data out not valid
(data out hold time)
Master/
Slave
Bypassed
T
C
+5
15
ns
Narrow
T
C
+55
65
ns
Wide
T
C
+106
116
ns
154
SS assertion to data out valid
(CPHA = 0)
Slave
T
C
+33
43
ns
157
First SCK sampling edge to HREQ output
deassertion
Slave
Bypassed
2.5
×
T
C
+30
55
ns
Narrow
2.5
×
T
C
+120
145
ns
Wide
2.5
×
T
C
+217
242
ns
158
Last SCK sampling edge to HREQ output not
deasserted (CPHA = 1)
Slave
Bypassed
2.5
×
T
C
+30
55
ns
Narrow
2.5
×
T
C
+80
105
ns
Wide
2.5
×
T
C
+136
161
ns
159
SS deassertion to HREQ output not deasserted
(CPHA = 0)
Slave
2.5
×
T
C
+30
55
ns
160
SS deassertion pulse width (CPHA = 0)
Slave
T
C
+6
16
ns
161
HREQ in assertion to first SCK edge
Master
Bypassed
0.5
×
t
SPICC
+
2.5
×
T
C
+43
121
ns
Narrow
0.5
×
t
SPICC
+
2.5
×
T
C
+43
174
ns
Wide
0.5
×
t
SPICC
+
2.5
×
T
C
+43
209
ns
162
HREQ in deassertion to last SCK sampling
edge (HREQ in set-up time) (CPHA = 1)
Master
0
0
ns
163
First SCK edge to HREQ in not asserted
(HREQ in hold time)
Master
0
0
ns
Note:
Periodically sampled, not 100% tested
Table 3-17 Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics
Mode
Filter
Mode
Expression
Min
Max
Unit
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DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic