參數(shù)資料
型號: DS80CH11
英文描述: System Energy Manager
中文描述: 系統(tǒng)能量管理器
文件頁數(shù): 76/88頁
文件大?。?/td> 598K
代理商: DS80CH11
DS80CH11
011200 76/88
7. During a 0 to 1 transition, a one–shot drives the ports hard for two oscillator clock cycles. This measurement
reflects port in transition mode. In addition, this specification applies to any of the Port 6.0–Port 6.3 pins when
the associated PWM channel is enabled.
8. Ports 1, 2, and 3 source transition current when being pulled down externally. Current reaches its maximum at
approximately 2V.
9. 0.45<V
IN
<V
CC
. Not a high impedance input. This port is a weak address holding latch in Bus Mode. Peak current
occurs near the input transition point of the latch, approximately 2V.
10.0.45<V
IN
<V
CC
. RST=V
CC
. This condition mimics operation of pins in I/O mode.
13.3 MICROCONTROLLER AC ELECTRICAL
CHARACTERISTICS
13.3.1 EXTERNAL PROGRAM MEMORY
CHARACTERISTICS
(0
°
C to 70
°
C; V
CC
=5.0
±
10%)
VARIABLE CLOCK
PARAMETER
SYMBOL
25 MHz
UNITS
MIN
MAX
MIN
MAX
Oscillator Frequency
1/t
CLCL
0
25
0
25
MHz
ALE Pulse Width
t
LHLL
55
(3t
CLCL
/2)–5
ns
Port 0 Address Valid to ALE Low
t
AVLL
15
(t
CLCL
/2)–5
ns
Address Hold after ALE Low
t
LLAX1
15
(t
CLCL
/2)–5
ns
ALE Low to Valid Instruction In
t
LLIV
80
2.5t
CLCL
–20
ns
ALE Low to PSEN Low
t
LLPL
15
(t
CLCL
/2)–5
ns
PSEN Pulse Width
t
PLPH
75
2t
CLCL
–5
ns
PSEN Low to Valid Instruction In
t
PLIV
60
2t
CLCL
–20
ns
Input Instruction Hold after PSEN
t
PXIX
0
0
ns
Input Instruction Float after PSEN
t
PXIZ
35
t
CLCL
–5
ns
Port 0 Address to Valid
Instruction In
t
AVIV1
100
3t
CLCL
–20
ns
Port 2 Address to Valid
Instruction In
t
AVIV2
115
3.5t
CLCL
–25
ns
PSEN Low to Address Float
t
PLAZ
0
0
ns
NOTES:
1. All signals rated over operating temperature.
2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR with 100 pF.
3. Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not dam-
age the parts, but will cause an increase in operating current.
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