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| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 77/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 77/88
13.3.2 MOVX USING STRETCH MEMORY CYCLES
(0
°
C to 70
°
C; V
CC
=5.0
±
10%)
PARAMETER
Data Access ALE Pulse Width
SYMBOL
t
LHLL2
VARIABLE CLOCK
MIN
1.5t
CLCL
–5
2t
CLCL
–5
0.5t
CLCL
–5
t
CLCL
–5
2t
CLCL
–5
t
MCS
–10
2t
CLCL
–5
t
MCS
–10
UNITS
ns
STRETCH
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
MAX
Address Hold after ALE Low for
MOVX Write
RD Pulse Width
t
LLAX2
ns
t
RLRH
ns
WR Pulse Width
t
WLWH
ns
RD Low to Valid Data In
t
RLDV
2t
CLCL
–20
t
MCS
–20
ns
Data Hold after Read
Data Float after Read
t
RHDX
t
RHDZ
0
ns
ns
t
CLCL
–5
2t
CLCL
–5
2.5t
CLCL
–20
t
MCS
+t
CLCL
–40
3t
CLCL
–20
t
MCS
+1.5t
CLCL
–20
3.5t
–20
t
MCS
+2t
CLCL
–20
0.5t
CLCL
+5
t
CLCL
+5
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
t
MCS
=0
t
MCS
>0
ALE Low to Valid Data In
t
LLDV
ns
Port 0 Address to Valid Data In
t
AVDV1
ns
Port 2 Address to Valid Data In
t
AVDV2
ns
ALE Low to RD or WR Low
t
LLWL
0.5t
CLCL
–5
t
CLCL
–5
t
CLCL
–5
2t
CLCL
–5
1.5t
CLCL
–5
2.5t
CLCL
–5
–5
t
CLCL
–5
2t
CLCL
–5
ns
Port 0 Address to RD or WR Low
t
AVWL1
ns
Port 2 Address to RD or WR Low
t
AVWL2
ns
Data Valid to WR Transition
Data Hold after Write
t
QVWX
t
WHQX
ns
ns
t
MCS
=0
t
MCS
>0
RD Low to Address Float
RD or WR High to ALE High
t
RLAZ
t
WHLH
–0.5t
CLCL
–5
10
t
CLCL
+5
ns
ns
0
t
CLCL
–5
t
MCS
=0
t
MCS
>0
NOTE:
t
MCS
is a time period related to the Stretch memory cycle selection. The following table shows the value of t
MCS
for
each Stretch selection.
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t
MCS
0
4 t
CLCL
8 t
CLCL
12 t
CLCL
16 t
CLCL
20 t
CLCL
24 t
CLCL
28 t
CLCL
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