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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 45/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 45/88
A/D CONVERTER BLOCK DIAGRAM
Figure 7–1
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
AVCC
AGND
VRH
VRL
10–BIT
SUCESSIVE
APPROXIMATION
A/D
8–CHAN.
ANALOG
INPUT
MUX
÷
N
PRESCALE
A/D MS
BYTE
A/D LS
BYTE
10–BIT LATCH
LOWER
LIMIT
UPPER
LIMIT
DIGITAL
WINDOW
COMPARATOR
START/BUSY
EOC
SS/CONT
CONTROL
LOGIC
STADC
SAMPLE
& HOLD
REFHI
REFLO
PWR
ACLK
CPU CLOCK
7.3
An A/D conversion is the process of assigning a digital
code to an analog input voltage. This code represents
the input value as a fraction of the reference voltage
range, which divided by the A/D converter into 1024
codes (10–bits). The reference voltage is connected to
the internal nodes called REFHI and REFLO as shown
in Figure 7–1.
REFERENCE OPTION
The REFHI and REFLO signals are connected to the
VRH and VRL pins, respectively.
The result can always be calculated from the following
formula:
Result = 1024 x ( V
IN
– REFLO) / ( REFHI – REFLO )
7.4
Figure 7–2 is a simplified block diagram of the succes-
sive approximation A/D converter. As with all succes-
sive approximation converters it contains a digital to
analog converter (DAC), a comparator, a successive
approximation register (SAR) and some control logic. A
conversion is initiated by the internal start signal issued
from the control logic. The successive approximation
logic sets bits of the DAC starting with bit 9 and proceed-
ing to bit 0 on each successive clock (ACLK). After each
bit is set the DAC output is compared with the sampled
analog input. If the DAC output is less than the analog
input the bit remains set. If the DAC output is greater
than the analog input the bit is reset. After all bits have
been tested and set or reset accordingly, the binary
value in SAR[9..0] is a digital representation of the ana-
log input value.
SAR A/D CONVERTER
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