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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 86/88頁 |
| 文件大小： | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 86/88
13.6 2–WIRE AC TIMING CHARACTERISTICS
(0
°
C to 70
°
C; V
CC
=5.0
±
10%)
OUTPUT
PARAMETER
SYMBOL
INPUT
START Condition Hold Time
t
STAH
> 14 t
CLK
(4)
> 1.0
μ
s
(1)
SCLx Low Time
t
SCL
> 16 t
CLK
(4)
> 1.3
μ
s
(1)
SCLx High Time
t
SCH
> 14 t
CLK
(4)
< 300 ns
(1)
> 0.6
μ
s
(1)
SCLx, SDAx Rise Time
t
SR
–
(2)
SCLx, SDAx Fall Time
t
SF
< 300 ns
(3)
< 300 ns
Data Setup Time
t
2DS
> 100 ns
> 250 ns
(1)
Data Hold Time
t
2DH
> 0 ns
> 8 t
CLK
– t
SF
(4)
> 600 ns
(1)
Repeated START Setup Time
t
RSTA
> 14 t
CLK
(4)
Repeated STOP Setup Time
t
RSTO
> 14 t
CLK
(4)
> 600 ns
(1)
Bus Free Time
t
2BF
> 14 t
CLK
(4)
> 1.3
μ
s
(1)
NOTES:
1. At 400Kbps. For other bit rates this value is multiplied by 400 / f
2W
.
2. Determined by the external bus line capacitance and the external bus line pull–up resistor; this must be < 300 ns
@ 400Kbps.
3. Spikes on the SDAx and SCLx lines with a duration of less than 50 ns will be filtered out. Maximum capacitance
on either SDAx and SCLx = 400 pF.
4. Where t
CLK
is the period of the XTAL oscillator and the instruction cycle rate is set to 4 clocks (default). The fre-
quency of the XTAL oscillator should be greater than 5 MHz for 400Kbps operation.
5. Both 2–Wire ports are identical and therefore only SDAx and SCLx are used here to simplify all notations.
SDAx = SDA1 or SDA2 and SCLx = SCL1 or SCL2 (“x” = 1 or 2).
2–WIRE SERIAL I/O TIMING
Figure 13–12
t
RSTO
t
SF
t
SR
t
RSTA
t
2DH
t
2DS
t
2BF
t
2DS
t
2DS
t
STAH
t
SR
t
SF
t
SCL
t
SCH
SDAx
SCLx
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