參數(shù)資料
型號： DS80CH11
英文描述： System Energy Manager
中文描述： 系統(tǒng)能量管理器
文件頁數(shù)： 34/88頁
文件大?。?/td> 598K
代理商： DS80CH11
DS80CH11
011200 34/88
6.2
The microcontroller interface to either 2–Wire serial port
consists of six Special Function Registers (SFR’s), per
REGISTER DESCRIPTION
Port, which are documented below. None of these reg-
isters are bit addressable.
6.2.1
2WFSx – 2–Wire Frequency Select Registers
2WFS1; SFR ADDR.=09CH, 2WFS2; SFR ADDR.=0D3H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The 2–Wire Frequency Select Registers are 8–bit read/
write registers which are used by the microcontroller to
set the 2–Wire clock data rate. The value programmed
into these registers sets the reload value for an 8–bit
auto–reload timer, which is clocked by the CPU
machine clock (t
MCLK
) through a divide–by–8 prescaler.
The CPU machine clock period is the oscillator clock
period (t
CLK
) multiplied times 4, 64, or 1024 as deter-
mined by the programming of the system clock divider
bits (CD1, CD0) in the PMR register. The 2–wire clock
frequency can therefore be calculated using the follow-
ing formula:
f
2Wx
= f
MCLK
/((8 * Reload) +2); t
2WCL
= 1 / f
2Wx
where
Reload=(2WFSx register value) for 2–255,
and
Reload=(256) for 2WFSx value=0
Reload=(1) is invalid
6.2.2
2WDATx – 2–Wire Data I/O Registers
2WDAT1; SFR ADDR.=09BH, 2WDAT2; SFR ADDR.=0D2H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The Data I/O Registers consist of transmit buffers and
the receive buffers. Both registers are located at SFR
address 9BH for Port 1 and D2H for Port 2. A write to
these locations results in a write to the transmit buffer
registers, while a read results in a read from the receive
buffer registers.
During transmit, a write to these locations results in
8–bits of data being transmitted on the 2–Wire bus when
either master or slave transmit mode is established.
When master or slave receive mode is in effect, 8–bits
are shifted in via the shift register and immediately
transferred to the receive buffer. All data is shifted MSB
first.
6.2.3
2WSADRx – 2–Wire Slave Address Registers
2WSADR1; SFR ADDR.=09AH, 2WSADR2; SFR ADDR.=0D1H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
–
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
SLA6–0 – Slave Address bits
SLA6–0 are used to establish the 7–bit address recog-
nized by the 2–Wire port when it is operating in slave
mode. The 7–bit slave address is MSB justified when it
is read or written by the firmware. When read, bit 0 is
always returned as a 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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