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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 46/88頁 |
| 文件大小： | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 46/88
SAR A/D SIMPLIFIED BLOCK DIAGRAM
Figure 7–2
CONTROL
LOGIC
ACLK
COMP
+
–
START
EOC
SUCCESSIVE
APPROXIMATION
REGISTER
10–BIT
SAMPLING
D/A CONVERTER
ANALOG IN
REFHI
REFLO
CVT
ZRO (SAMPLE)
RESOLUTION
SAR [9..0]
OFFSET
2
7.5
An internal clock signal called ACLK is used to clock the
successive approximation logic in performing the A/D
conversion. ACLK is derived from the microcontroller
clock signal through divide–down logic. A total of 16
clock cycles are required to perform the conversion.
The minimum ACLK period is 1
μ
s, a faster clock can
result in erroneous results. At the other extreme, the
maximum clock period is 6.25
μ
s due the dynamic
nature of the internal sample–hold circuitry.
CONVERSION TIME
In order to meet these requirements and accommodate
a wide range of CPU clock frequencies a programmable
prescaler is provided to generate appropriate converter
clock (ACLK) from the CPU clock.
Based on the micro’s CPU clock, the ACLK frequency
can be set to one of 16 values via the four A/D clock
prescaler (APS) bits in the ADCON2 register. This
results in a conversion clock frequency as given by the
formula below:
t
ACLK
= t
MCLK
(N+1)
where t
ACLK
is the analog clock period, t
MCLK
is the CPU
machine clock period, and N is the clock prescale value
ranging from 0 to 15 as programmed in the APS bits.
The CPU machine clock period is the oscillator clock
period (t
CLK
) multiplied times 4, 64, or 1024 as deter-
mined by the programming of the system clock divider
bits (CD1, CD0) in the PMR register.
The resulting t
ACLK
must meet the criteria of
1.00
μ
s < t
ACLK
< 6.25
μ
s
Table 7–1 gives a set of conversion times at usable A/D
clock prescaler settings for a range of microcontroller
clock frequencies, assuming that the microcontroller
machine clock is at its default value of 4 crystal clock
periods.
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