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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 12/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 12/88
PIN
SYMBOL
DESCRIPTION
8
7
6
5
4
3
2
1
P9.0 (KSO.8)
P9.1 (KSO.9)
P9.2 (KSO.10)
P9.3 (KSO.11)
P9.4 (KSO.12)
P9.5 (KSO.13)
P9.6 (KSO.14)
P9.7 (KSO.15)
Port 9 / KSO.15–8:
– I/O. Port 9 provides eight lines of open–drain psuedo–bi–direc-
tional I/O port pins. Typically, these lines are used for key–scan outputs.
60
61
62
63
64
65
66
67
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
Port10:
–I/O. Port 10 provides eight lines of general purpose Input or Output.
41
PM1CS
Power Management #1 Chip Select:
(Input, active low). This is a chip select signal
used to enable the power management #1 host interface port.
59
PM2CS
Power Management #2 Chip Select:
(Input, active low). This is a chip select signal
used to enable the power management #2 host interface port.
107
PSEN
Program Store Enable:
Output. This signal goes low when off–chip program memory
is being accessed via Ports 0 and 2. It is commonly connected to optional external ROM
memory as a chip enable. PSEN will provide an active low pulse and is driven high when
external ROM is not being accessed.
105
RST
Reset:
Input, active high The RST input pin contains a Schmitt voltage input to recog-
nize external active high Reset inputs. The pin also employs an internal pull–down
resistor to allow for a combination of wired OR external Reset sources. An RC is not
required for power–up, as the controller provides this function internally.
55
54
53
52
51
50
49
48
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
System Data Bus:
(Bi–directional). SD7–0 are data bus lines used for data transfers
between the host processor and the keyboard interface buffer and power management
#1 and #2 interface buffers.
39
SMI1
System Management Interrupt #1:
(Output, active low). This signal is driven low
when the power management #1 host interface data buffer contains data to be read by
the host. SMI1 will be returned to a High Level when host reads the power management
#1 data buffer register.
58
SMI2
System Management Interrupt #2:
(Output, active low). This signal is driven low
when the power management #2, host interface data buffer contains data to be read by
the host. SMI2 will be returned to a high level when the host reads the power manage-
ment #2 data buffer register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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