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參數(shù)資料
| 型號： | DS80CH11 |
| 英文描述： | System Energy Manager |
| 中文描述： | 系統(tǒng)能量管理器 |
| 文件頁數(shù)： | 24/88頁 |
| 文件大小： | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 24/88
4.0
MEMORY RESOURCES
4.1
The SEM contains the following memory resources and
features:
OVERVIEW
256 bytes of on–chip direct (scratchpad) RAM
256 bytes of on–chip MOVX data RAM
Off–chip program and data memory expansion
Software enable/disable of on–chip data memory
4.2
Unlike many 8051 derivatives, the SEM contains on–
chip data memory. Although physically on–chip, soft-
ware accesses this area in the same way off–chip data
memory is accessed: via the MOVX instruction. The
256 bytes of SRAM is located between address 0000h
and 00FFh.
DATA MEMORY ACCESS
Access to the on–chip data RAM is optional under soft-
ware control. When enabled by software, the data
SRAM is between 0000h and 00FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 256
automatically go to external memory through Ports
0 & 2.
When disabled, the 256 bytes of memory area is trans-
parent to the system memory map. Any MOVX directed
to the space between 0000h and FFFFh goes to the
expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the SEM to drop into an
existing system that uses these addresses for other
hardware and still have full compatibility.
The on–chip data area is selected by software using two
bits in the Power Management Register at location C4h.
This selection is dynamically programmable. Thus
access to the on–chip area becomes transparent to
reach off–chip devices at the same addresses. The
control bits are DME1 (PMR.1) and DME0 (PMR.0).
Their operation is described in Table 4–1.
DATA MEMORY ACCESS CONTROL
Table 4–1
DME1
DME0
DATA MEMORY ADDRESS
MEMORY FUNCTION
0
0
0000h – FFFFh
External Data Memory (Default condition)
0
1
0000h – 00FFh
0100h – FFFFh
Internal SRAM Data Memory
External Data Memory
1
0
Reserved
Reserved
1
1
0000h – 00FFh
0100h – FFFBh
FFFCh
FFFDh – FFFFh
Internal SRAM Data Memory
Reserved – no external access
Read access to the status of lock bits
Reserved – no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security
lock bits LB3–LB1. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read
only.
4.2.1
The SEM allows software to adjust the speed of off–chip
data memory access. The micro is capable of perform-
ing the MOVX in as little as two instruction cycles. The
on–chip SRAM uses this speed and any MOVX instruc-
tion directed internally uses two cycles. However, the
time can be stretched for interface to external devices.
This allows access to both fast memory and slow
memory or peripherals with no glue logic. Even in high–
speed systems, it may not be necessary or desirable to
Stretch Memory Cycle
perform off–chip data memory access at full speed. In
addition, there are a variety of memory mapped periph-
erals such as LCDs or UARTs that are slow.
Operation of the Stretch MOVX function is fully docu-
mented in the Dallas High Speed Micro User’s Guide.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS80CH11+E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11+E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11+E02 System Energy Managers |
| DS80CH11-E02 | 制造商:Maxim from Components Direct 功能描述:MAXIM DS80CH11-E02 SYSTEM ENERGY MANAGERS - Trays 制造商:Maxim 功能描述:Maxim DS80CH11-E02 System Energy Managers |
| DS80E100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
| DS80EP100_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables |
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