參數(shù)資料
型號(hào)： DS80CH11
英文描述： System Energy Manager
中文描述： 系統(tǒng)能量管理器
文件頁(yè)數(shù)： 41/88頁(yè)
文件大?。?/td> 598K
代理商： DS80CH11
DS80CH11
011200 41/88
programming the 2WSADRx register with the address
value left–justified. The ANAKx bit should be cleared to
0 to allow a positive acknowledge bit to be issued when
the SEM’s slave address is received.
SLAVE RECEIVE OPERATION TIMING
Figure 6–6
SLAVE ADDR.
R/W
A
SDAx/SCLx
P
X/Rx BIT
RXIx BIT
ACKSx BIT
ANAKx BIT
éé
éé
éé
S
DATA
A
DATA
A
DATA
A/A
0
ADMx BIT
RCV BUF.
READ
RSTOx BIT
The transfer is initiated by the external master beginning
with either a START or Repeat START condition, fol-
lowed by the transmission of the SEM’s slave address
with the direction bit cleared to 0. This byte will be
shifted in and loaded into the receive buffer register at
the time the acknowledge bit is returned to the master,
resulting in RXIx being set to 1. In addition, an address
match condition will occur as indicated by the ADMx flag
set to 1. Upon detecting these flags, the firmware
should respond by reading the receive buffer in order to
determine if the programmed slave address or the gen-
eral call address was received. Following the read of
the buffer, the RXIx flag must be cleared. Also at this
time the firmware should insure that the 2WIFx bit is
cleared to 0, so that the interrupt flag will be set in
response to subsequent received data byte(s) and
STOP condition.
Upon the receipt of the first data byte, the RXIx bit will be
set at the time the acknowledge bit is transmitted. The
firmware should read the incoming byte from the receive
buffer register followed by a clear of RXIx to 0. Subse-
quent incoming data bytes are handled in the same
manner. If desired, the ANAKx bit can be set to cause a
negative acknowledge to be issued upon receipt of the
next byte.
When the last byte of data has been sent, the bus mas-
ter will issue a STOP condition, which will result in the
RSTOx flag set to a 1. At this time, the port hardware
returns to the not–addressed slave mode.
6.3.4
Figure 6–7 illustrates the timing for Slave Transmit
mode operation. In this mode the SEM, addressed as a
slave, transfers one or more bytes to the bus master.
Slave Transmit
The transfer is initiated by the external master beginning
with either a START or Repeat START condition, fol-
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