參數(shù)資料
型號(hào)： DATASHEET
英文描述： ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE
中文描述： ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口
文件頁(yè)數(shù)： 70/74頁(yè)
文件大?。?/td> 897K
代理商： DATASHEET
ST10F168
70/74
Figure 29 :
CLKOUT and READY
Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling
point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t
37
in order to be safely synchronized. This is guaranteed, if READY is removed in response
to the command (see Note 4)).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this
delay is zero.
7. The next external bus cycle may start here.
t
30
t
34
t
35
t
36
t
35
t
36
t
58
t
59
t
58
t
59
wait state
READY
MUX / Tristate 6)
t
32
t
33
t
29
Running cycle 1)
t
31
t
37
3)
3)
5)
t
604)
6)
2)
7)
3)
3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY
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