參數(shù)資料
型號(hào)： DATASHEET
英文描述： ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE
中文描述： ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口
文件頁(yè)數(shù)： 69/74頁(yè)
文件大小： 897K
代理商： DATASHEET
ST10F168
69/74
20.5.12 - CLKOUT and READY
V
DD
= 5V ±10%, V
SS
= 0V, for Q6 version : T
A
= -40, +85°C and for Q3 version T
A
= -40, +125°C, C
L
= 100pF,
unless otherwise specified
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivating READY.
The 2t
A
and t
C
refer to the next following bus cycle, t
F
refers to the current bus cycle.
Table 26 :
CLKOUT and READY characteristics
Symbol
Parameter
Max. CPU Clock
25MHz
Variable CPU Clock
1/2 TCL = 1 to 25MHz
Unit
Minimum
Maximum
Minimum
Maximum
t
29
CC
CLKOUT cycle time
40
40
2TCL
2TCL
ns
t
30
CC
CLKOUT high time
14
–
TCL – 6
–
ns
t
31
CC
CLKOUT low time
10
–
TCL – 10
–
ns
t
32
CC
CLKOUT rise time
–
4
–
4
ns
t
33
CC
CLKOUT fall time
–
4
–
4
ns
t
34
CC
CLKOUT rising edge to ALE falling
edge
-3 + t
A
+7 + t
A
-3 + t
A
7 + t
A
ns
t
35
SR
Synchronous READY setup time to
CLKOUT
14
–
14
–
ns
t
36
SR
Synchronous READY hold time after
CLKOUT
4
–
4
–
ns
t
37
SR
Asynchronous READY low time
54
–
2TCL + 14
–
ns
t
58
SR
Asynchronous READY setup time
1
14
–
14
–
ns
t
59
SR
Asynchronous READY hold time
1
4
–
4
–
ns
t
60
SR
Async. READY hold time after RD, WR
high (Demultiplexed Bus)
2
0
0 + 2t
A
+ tC + t
F
2
0
TCL - 20
+ 2t
A
+ tC + t
F
2
ns
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