參數(shù)資料
型號： DATASHEET
英文描述： ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE
中文描述： ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口
文件頁數(shù)： 58/74頁
文件大?。?/td> 897K
代理商： DATASHEET
ST10F168
58/74
Note:
1. Partially tested, guaranteed by design characterization.
t
23
CC
Data hold after WR
26 + t
F
–
2TCL - 14 + t
F
–
ns
t
25
CC
ALE rising edge after RD, WR
26 + t
F
–
2TCL - 14 + t
F
–
ns
t
27
CC
Address / Unlatched CS hold
after RD, WR
26 + t
F
–
2TCL - 14 + t
F
–
ns
t
38
CC
ALE falling edge to Latched CS
-4 - t
A
10 - t
A
-4 - t
A
10 - t
A
ns
t
39
SR
Latched CS low to Valid Data In
–
40 + t
C
+ 2t
A
–
3TCL - 20
+ t
C
+ 2t
A
ns
t
40
CC
Latched CS hold after RD, WR
46 + t
F
–
3TCL - 14 + t
F
–
ns
t
42
CC
ALE fall. edge to RdCS, WrCS
(with RW delay)
16 + t
A
–
TCL - 4 + t
A
–
ns
t
43
CC
ALE fall. edge to RdCS, WrCS
(no RW delay)
-4 + t
A
–
-4 + t
A
–
ns
t
44
CC
Address float after RdCS, WrCS
1
(with RW delay)
–
0
–
0
ns
t
45
CC
Address float after RdCS, WrCS
1
(no RW delay)
–
20
–
TCL
ns
t
46
SR
RdCS to Valid Data In (with RW
delay)
–
16 + t
C
–
2TCL - 24 + t
C
ns
t
47
SR
RdCS to Valid Data In (no RW
delay)
–
36 + t
C
–
3TCL - 24 + t
C
ns
t
48
CC
RdCS, WrCS Low Time (with RW
delay)
30 + t
C
–
2TCL - 10 + t
C
–
ns
t
49
CC
RdCS, WrCS Low Time (no RW
delay)
50 + t
C
–
3TCL - 10 + t
C
–
ns
t
50
CC
Data valid to WrCS
26 + t
C
–
2TCL - 14+ t
C
–
ns
t
51
SR
Data hold after RdCS
0
–
0
–
ns
t
52
SR
Data float after RdCS
1
–
20 + t
F
–
2TCL - 20 + t
F
ns
t
54
CC
Address hold after RdCS, WrCS
20 + t
F
–
2TCL - 20 + t
F
–
ns
t
56
CC
Data hold after WrCS
20 + t
F
–
2TCL - 20 + t
F
–
ns
Table 24 :
Multiplexed bus characteristics (continued)
Symbol
Parameter
Maximum CPU Clock
25MHz
Variable CPU Clock
1/2 TCL = 1 to 25MHz
Unit
Minimum
Maximum
Minimum
Maximum
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