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| 型號： | DATASHEET |
| 英文描述： | ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE |
| 中文描述： | ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口 |
| 文件頁數(shù)： | 39/74頁 |
| 文件大?。?/td> | 897K |
| 代理商： | DATASHEET |
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ST10F168
39/74
Figure 11 :
Synchronous Warm Reset: Long low pulse on
RSTIN
Notes: 1. RSTIN rising edge to internal latch of Port0 is 3CPU
clock cycles (6 TCL) if the PLL is bypassed and the
prescaler is on (f
CPU
= f
XTAL
/ 2), else it is 4 CPU clock
cycles (8 TCL).
2. If during the reset condition (RSTIN low), Vpp voltage
drops below the threshold voltage (about 2.5V for 5V
operation), the asynchronous reset is then immediately
entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of
SYSCON register) was previously set by soft-ware. Bit
BDRSTEN is cleared after reset.
17.3 - Software Reset
A software reset sequence can be triggered at
any time by the protected SRST (software reset)
instruction. This instruction can be deliberately
executed within a program, e.g. to leave bootstrap
loader mode, or on a hardware trap that reveals
system failure.
On execution of the SRST instruction, the internal
reset sequence is started. The microcontroller
behaviour is the same as for a synchronous reset,
except that only bit P0.12...P0.8 are latched at the
end of the reset sequence, while previously
latched, bit P0.7...P0.2 are cleared.
17.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during
the initialization, or serviced regularly during pro-
gram execution, it will overflow and trigger the
reset sequence.
Unlike hardware and software resets, the watch-
dog reset completes a running external bus cycle
if this bus cycle either does not use READY, or if
READY is sampled active (low) after the pro-
grammed wait states. When READY is sampled
inactive (high) after the programmed wait states
the running external bus cycle is aborted. Then
the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset
sequence and bit P0.7...P0.2 are cleared.
17.5 - Reset Circuitry
Internal reset circuitry is described in Figure 13.
The
RSTIN
pin provides an internal pullup resistor
of 50K
to 250K
(The minimum reset time must
be calculated using the lowest value). It also pro-
vides a programmable (BDRSTEN bit of SYSCON
register) pulldown to output internal reset state
signal (synchronous reset, watchdog timer reset
or software reset).
This bidirectional reset function is useful in appli-
cations where external devices require a reset sig-
nal but cannot be connected to
RSTOUT
pin.
This is the case of an external memory running
codes before EINIT ( end of initialization) instruc-
tion is executed.
RSTOUT
pin is pulled high only
when EINIT is executed.
The V
PP
pin provides an internal weak pulldown
resistor which discharges external capacitor at a
typical rate of 200
μ
A. If bit PWDCFG of SYSCON
register is set, an internal pullup resistor is acti-
vated at the end of the reset sequence. This pul-
lup will charge any capacitor connected on V
PP
pin.
CPU Clock
RSTIN
V
PP
RSTOUT
ALE
Port0
Internal
Reset
Signal
Latching point of Port0
for system start-up configuration
6 or 8 TCL
1
4 TCL
12 TCL
1024 TCL
Internally pulled low
3
Reset Configuration
2
V
PP
> 2.5V Asynchronous Reset not entered.
200
μ
A Discharge
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