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| 型號： | DATASHEET |
| 英文描述： | ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE |
| 中文描述： | ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口 |
| 文件頁數(shù)： | 56/74頁 |
| 文件大?。?/td> | 897K |
| 代理商： | DATASHEET |
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ST10F168
56/74
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes f
CPU
to keep it
locked on f
XTAL
. The relative deviation of TCL is
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 19 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation D
N
:
where N = number of consecutive TCL periods
and 1
≤
N
≤
40. So for a period of 3 TCL periods
(N = 3):
D
3
=
4 - 3/15 = 3.8%
3TCL
min
=
3TCL
NOM
x (1 - 3.8/100)
=
3TCL
NOM
x 0.962
3TCL
min
=
(57.72ns at f
CPU
= 25MHz)
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible (see Figure 19).
20.5.8 - External Clock Drive XTAL1
V
DD
= 5V ± 10%, V
SS
= 0V, for Q6 version : T
A
= -40, +85°C and for Q3 version T
A
= -40, + 125°C, unless
otherwise specified.
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.
2. The input clock signal must reach the defined levels V
IL
and V
IH2
.
TCLMIN
TCLNOM
1
DN
100
-------------
–
×
=
DN
4
N 15
)
%
[
]
–
(
±
=
Figure 19 :
Approximated maximum PLL jitter
Symbol
Parameter
f
CPU
= f
XTAL
f
CPU
= f
XTAL
/ 2
f
CPU
= f
XTAL
x N
N = 1.5 / 2 / 2.5 / 3 / 4 / 5
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
OSC
SR
Oscillator period
40
1
18
2
18
2
1000
20
6
2
6
2
500
40 x N
10
2
10
2
100 x N
ns
t
1
t
2
t
3
t
4
SR
High time
–
–
–
ns
SR
Low time
–
–
–
ns
SR
Rise time
–
10
2
10
2
–
6
3
6
2
–
10
2
10
2
ns
SR
Fall time
–
–
–
ns
Figure 20 :
External clock drive XTAL1
32
16
8
4
2
±
1
±
2
±
3
±
4
Max.jitter [%]
N
This approximated formula is valid for
1 < N < 40 and 10MHz < f
CPU
< 25MHz.
t
1
t
3
t
4
V
IH2
t
2
t
OSC
V
IL
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