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| 型號： | DATASHEET |
| 英文描述： | ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE |
| 中文描述： | ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口 |
| 文件頁數(shù)： | 54/74頁 |
| 文件大?。?/td> | 897K |
| 代理商： | DATASHEET |
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ST10F168
54/74
20.5.2 - Definition of Internal Timing
The internal operation of the ST10F168 is
controlled by the internal CPU clock f
CPU
. Both
edges of the CPU clock can trigger internal (e.g.
pipeline) or external (e.g. bus cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock,
called “TCL” (see Figure 18).
Figure 18 :
Generation Mechanisms for the CPU Clock
The CPU clock signal can be generated by
different mechanisms. The duration of TCL and its
variation (and also the derived external timing)
depends on the mechanism used to generate
f
CPU
. This influence must be regarded when
calculating the timings for the ST10F168.
The example for PLL operation shown in the
Figure 18 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock
is selected during reset by the logic levels on pins
P0.15-13 (P0H.7-5).
20.5.3 - Clock Generation Modes
The Table 23 associates the combinations of these three bit with the respective clock generation mode.
Notes: 1. The external clock input range refers to a CPU clock range of 1...25MHz.
2. The maximum depends on the duty cycle of the external clock signal.
3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial
resistance of the crystal is less than 40
. However, higher frequencies can be applied with an external clock source on pin XTAL1,
but in this case, the input clock signal must reach the defined levels V
IL
and V
IH2.
Table 23 :
CPU Frequency Generation
P0H.7 P0H.6 P0H.5 CPU Frequency f
CPU
= f
XTAL
x F External Clock Input Range
1
Notes
1
1
1
f
XTAL
x 4
2.5 to 6.25MHz
Default configuration
1
1
0
f
XTAL
x 3
3.33 to 8.33MHz
1
0
1
f
XTAL
x 2
5 to 12.5MHz
1
0
0
f
XTAL
x 5
2 to 5MHz
0
1
1
f
XTAL
x 1
1 to 25MHz
Direct drive
2
0
1
0
f
XTAL
x 1.5
6.66 to 16.6MHz
0
0
1
f
XTAL
/ 2
2 to 50MHz
CPU clock via prescaler
3
0
0
0
f
XTAL
x 2.5
4 to 10MHz
TCL TCL
TCL TCL
f
CPU
f
XTAL
f
CPU
f
XTAL
Phase locked loop operation
Direct Clock Drive
TCL
TCL
f
CPU
f
XTAL
Prescaler Operation
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