參數(shù)資料
型號(hào)： DATASHEET
英文描述： ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE
中文描述： ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口
文件頁(yè)數(shù)： 64/74頁(yè)
文件大小： 897K
代理商： DATASHEET
ST10F168
64/74
Notes: 1. RW-delay and t
A
refer to the following bus cycle.
2. Partially tested, guaranteed by design characterization.
3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
t
39
SR
Latched CS low to Valid Data In
–
40 + t
C
+ 2t
A
–
3TCL - 20
+ t
C
+ 2t
A
ns
t
41
CC
Latched CS hold after RD, WR
6 + t
F
–
TCL - 14 + t
F
–
ns
t
82
CC
Address setup to RdCS, WrCS
(with RW-delay)
26 + 2t
A
–
2TCL - 14 + 2t
A
–
ns
t
83
CC
Address setup to RdCS, WrCS
(no RW-delay)
6 + 2t
A
–
TCL -14 + 2t
A
–
ns
t
46
SR
RdCS to Valid Data In (with
RW-delay)
–
16 + t
C
–
2TCL - 24 + t
C
ns
t
47
SR
RdCS to Valid Data In (no
RW-delay)
–
36 + t
C
–
3TCL - 24 + t
C
ns
t
48
CC
RdCS, WrCS Low Time (with
RW-delay)
30 + t
C
–
2TCL - 10 + t
C
–
ns
t
49
CC
RdCS, WrCS Low Time (no
RW-delay)
50 + t
C
–
3TCL - 10 + t
C
–
ns
t
50
CC
Data valid to WrCS
26 + t
C
–
2TCL - 14 + t
C
–
ns
t
51
SR
Data hold after RdCS
0
–
0
–
ns
t
53
SR
Data float after RdCS (with
RW-delay)
2
–
20 + t
F
–
2TCL - 20 + t
F
ns
t
68
SR
Data float after RdCS (no
RW-delay)
2
–
0 + t
F
–
TCL - 20 + t
F
ns
t
55
CC
Address hold after RdCS, WrCS
-10 + t
F
–
-10 + t
F
–
ns
t
57
CC
Data hold after WrCS
6 + t
F
–
TCL - 14 + t
F
–
ns
Table 25 :
Demultiplexed bus characteristics (continued)
Symbol
Parameter
Maximum
CPU Clock = 25MHz
Variable CPU Clock
1/2 TCL = 1 to 25MHz
Unit
Minimum
Maximum
Minimum
Maximum
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