參數(shù)資料
型號(hào)： DATASHEET
英文描述： ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE
中文描述： ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口
文件頁(yè)數(shù)： 57/74頁(yè)
文件大小： 897K
代理商： DATASHEET
ST10F168
57/74
20.5.9 - Memory Cycle Variables
The tables below use three variables which are derived from the BUSCONx registers and which
represent the special characteristics of the programmed memory cycle. The following table describes
how these variables are computed.
20.5.10 - Multiplexed Bus
V
DD
= 5V ±10%, V
SS
= 0V, for Q6 version : T
A
= -40, +85°C and for Q3 version T
A
= -40, + 125°C, C
L
= 100pF,
ALE cycle time = 6 TCL + 2t
A
+ t
C
+ t
F
(120ns at 25MHz CPU clock without wait states), unless otherwise
specified.
Symbol
Description
Values
t
A
t
C
t
F
ALE Extension
TCL x <ALECTL>
Memory Cycle Time wait states
2TCL x (15 - <MCTC>)
Memory Tristate Time
2TCL x (1 - <MTTC>)
Table 24 :
Multiplexed bus characteristics
Symbol
Parameter
Maximum CPU Clock
25MHz
Variable CPU Clock
1/2 TCL = 1 to 25MHz
Unit
Minimum
Maximum
Minimum
Maximum
t
5
CC
ALE high time
10 + t
A
–
TCL - 10 + t
A
–
ns
t
6
CC
Address setup to ALE
4 + t
A
–
TCL - 16+ t
A
–
ns
t
7
CC
Address hold after ALE
10 + t
A
–
TCL - 10 + t
A
–
ns
t
8
CC
ALE falling edge to RD, WR
(with RW-delay)
10 + t
A
–
TCL - 10 + t
A
–
ns
t
9
CC
ALE falling edge to RD, WR
(no RW-delay)
-10 + t
A
–
-10 + t
A
–
ns
t
10
CC
Address float after RD, WR
1
(with RW-delay)
–
6
–
6
ns
t
11
CC
Address float after RD, WR
1
(no RW-delay)
–
26
–
TCL + 6
ns
t
12
CC
RD, WR low time (with RW-delay)
30 + t
C
–
2TCL - 10 + t
C
–
ns
t
13
CC
RD, WR low time (no RW-delay)
50 + t
C
–
3TCL - 10 + t
C
–
ns
t
14
SR
RD to valid data in (with RW-delay)
–
20 + t
C
–
2TCL - 20+ t
C
ns
t
15
SR
RD to valid data in (no RW-delay)
–
40 + t
C
–
3TCL - 20+ t
C
ns
t
16
SR
ALE low to valid data in
–
40 + t
A
+ t
C
–
3TCL - 20
+ t
A
+ t
C
ns
t
17
SR
Address / Unlatched CS to valid
data in
–
50 + 2t
A
+ t
C
–
4TCL - 30
+ 2t
A
+ t
C
ns
t
18
SR
Data hold after RD rising edge
0
–
0
–
ns
t
19
SR
Data float after RD
1
–
26 + t
F
–
2TCL - 14 + t
F
ns
t
22
CC
Data valid to WR
20 + t
C
–
2TCL - 20 + t
C
–
ns
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