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參數(shù)資料
| 型號： | DATASHEET |
| 英文描述： | ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE |
| 中文描述： | ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口 |
| 文件頁數(shù)： | 40/74頁 |
| 文件大?。?/td> | 897K |
| 代理商： | DATASHEET |
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ST10F168
40/74
The simplest way to reset the ST10F168 is to
insert a capacitor C1 between
RSTIN
pin and V
SS
,
and a capacitor between V
PP
pin and V
SS
(C0)
with a pullup resistor R0 between V
PP
pin and
V
CC
. The input
RSTIN
provides an internal pullup
device equalling a resistor of 50k
to 150k
(the
minimum reset time must be determined by the
lowest value). Select C1 that produce a sufficient
discharge time to permit the internal or external
oscillator and / or internal PLL to stabilize.
To insure correct power-up reset with controlled
supply current consumption, specially if clock sig-
nal requires a long period of time to stabilized, an
asynchronous hardware reset is required during
power-up. It is recommended to connect the exter-
nal R0C0 circuit shown in Figure 12 to the V
PP
pin. On power-up, the logical low level on V
PP
pin
forces an asynchronous harware reset when
RSTIN
is asserted.
The external pullup R0 will then charge the capac-
itor C0. Note that an internal pulldown device on
V
PP
pin is turned on when
RSTIN
pin is low, and
causes the external capacitor (C0) to begin dis-
charging at a typical rate of 100
μ
A to 200
μ
A. With
this mechanism, after power-up reset, short low
pulses applied on
RSTIN
produce synchronous
hardware reset. If
RSTIN
is asserted longer than
the time needed for C0 to be discharged by the
internal pulldown device, then the device is forced
in an asynchronous reset. This mechanism
insures recovery from very catastrophic failure.
Figure 12 :
Minimum External Reset Circuitry
RSTOUT
V
PP
RSTIN
C1
a) Hardware
Reset
V
CC
+
C0
R0
ST10F168
b) For Power-up
Reset
(and Interruptible
Power-down
mode)
External Hardware
+
Figure 13 :
Internal (simplified) Reset Circuitry
RSTOUT
EINIT Instruction
Trigger
Clr
Clock
Reset State
Machine
Internal
Reset
Signal
Reset Sequence
(512 CPU Clock Cycles)
SRST instruction
watchdog overflow
RSTIN
V
CC
BDRSTEN
V
CC
V
PP
(Flash device)
V
PP
Weak Pulldown
(~200
μ
A)
From/to Exit
Powerdown
Circuit
Asynchronous
Reset
Clr
Q
Set
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