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參數(shù)資料
| 型號(hào)： | DATASHEET |
| 英文描述： | ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE |
| 中文描述： | ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口 |
| 文件頁數(shù)： | 19/74頁 |
| 文件大?。?/td> | 897K |
| 代理商： | DATASHEET |
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ST10F168
19/74
6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. Additional hardware has been added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.
Most of the ST10F168’s instructions can be exe-
cuted in one instruction cycle which requires
62.5ns at 32MHz CPU clock. For example, shift
and rotate instructions are processed in one
instruction cycle independent of the number of bit
to be shifted. Multiple-cycle instructions have
been optimized: branches are carried out in 2
cycles, 16 x 16-bit multiplication in 5 cycles and a
32/16 bit division in 10 cycles.The jump cache
reduces the execution time of repeatedly per-
formed jumps in a loop, from 2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run
the current context. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip RAM area. A Context Pointer (CP) regis-
ter determines the base address of the active reg-
ister bank to be accessed by the CPU. The
number of register banks is only restricted by the
available internal RAM space. For easy parameter
passing, one register bank may overlap others.
A system stack of up to 2048 Byte stores tempo-
rary data. The system stack is allocated in the
on-chip RAM area, and it is accessed by the CPU
via the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly com-
pared against the stack pointer value on each
stack access, for the detection of a stack overflow
or underflow.
Figure 5 :
CPU Block Diagram
32
Internal
RAM
2K Byte
General
Purpose
Registers
R0
R15
MDH
MLD
Barrel-Shift
CP
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
CPU
256K Byte
Flash
memory
16
16
Bank
n
Bank
i
Bank
0
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