參數(shù)資料
型號: DATASHEET
英文描述: ST10F168 - 16-BIT MCU - 8KB RAM - 256KB FLASH MEMORY - 111 I/O - 1 CAN 2.0B INTERFACE
中文描述: ST10F168 - 16位MCU - 8KB的內(nèi)存- 256KB的快閃記憶體- 111的I / O - 1 CAN 2.0B總線接口
文件頁數(shù): 51/74頁
文件大小: 897K
代理商: DATASHEET
ST10F168
51/74
Notes: 1. ST10F168 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These
low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current
is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The
current specified in column “Test Conditions” is delivered in all cases.
2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the
voltage results from the external circuitry.
3. Partially tested, guaranteed by design characterization.
4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified
range (i.e. V
OV
> V
DD
+0.5V or V
OV
< -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The
supply voltage must remain within the specified limits.
5. The maximum current may be drawn while the respective signal line remains inactive.
6. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for
CS output and the open drain function is not enabled.
7. The minimum current must be drawn in order to drive the respective signal line active.
8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These
parameters are tested at V
DD
max and 25MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is
configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during
reset. After reset, Port 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15 wait-state, R/W
delay, memory tristate wait state, normal ALE. Peripherals are not activated.
9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These
parameters are tested at V
DD
max and 25MHz CPU clock with all outputs disconnected and all inputs at V
IL
or V
IH
.
10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at
V
DD
– 0.1V to V
DD
, V
REF
= 0V, all outputs (including pins configured as outputs) disconnected.
11. Apply 12V on V
PP
10ms after V
DD
is stable at power up. V
PP
pin must be switched to 0V before to switch off V
DD
(5V).
I
OZ2
I
OV
CC Input leakage current (all other)
0V < V
IN
< V
DD
3
4
±
1
μ
A
SR Overload current
CC RSTIN pull-up resistor
3
Read / Write inactive current
6
Read / Write active current
6
ALE inactive current
6
ALE active current
6
Port 6 inactive current
6
±
5
mA
R
RST
I
RWH
5
I
RWL
7
I
ALEL
6
I
ALEH
6
I
P6H
6
I
P6L
7
I
P0H
6
I
P0L
7
I
IL
0V < V
IN
< V
ILmax
50
250
k
V
OUT
= 2.4V
V
OUT
= V
OLmax
-40
μ
A
-500
μ
A
V
OUT
= V
OLmax
40
μ
A
V
OUT
= 2.4V
V
OUT
= 2.4V
V
OUT
= V
OL1max
600
μ
A
-40
μ
A
Port 6 active current
6
-500
μ
A
Port 0 configuration current
6
V
IN
= V
IHmin
-10
μ
A
V
IN
= V
ILmax
0V < V
IN
< V
DD
-100
μ
A
CC XTAL1 input current
±
20
μ
A
C
IO
CC Pin capacitance
6
(digital inputs / outputs)
f = 1MHz,
T
A
= 25°C
RSTIN = V
IH1
f
CPU
in [MHz]
8
10
pF
I
CC
Power supply current
20 + 6 x f
CPU
mA
I
ID
Idle mode supply current
RSTIN = V
IH1
f
CPU
in [MHz]
9
V
DD
= 5.5V
10
20 + 3 x f
CPU
mA
I
PD
Power-down mode supply current
100
μ
A
I
PPR
V
PP
Read Current
V
PP
< V
DD
200
μ
A
I
PPW
V
PP
Programming / Erasing Current
3
V
PP
= 12V,
f
CPU
= 25MHz
20
mA
V
PP11
V
PP
during Programming / Erasing Operations
11,4
12,6
V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
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