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PFWKPU
PFSCHEN
IVCT
NMISTAT
EXNMI
ISTAT0
ISTAT1
IENAM
IENAM1
U1TBUF
U1RBUF
U1ICTRL
U1STAT
U1FRS
U1MDSL
U1BAUD
U1PSR
MWDAT
MWCTL1
MWCTL2
MWCTL3
MWSTAT
U2TBUF
U2RBUF
U2ICTRL
U2STAT
U2FRS
U2MDSL
U2BAUD
U2PSR
PIALT
PIDIR
PIDIN
PIDOUT
PIWKPU
PISCHEN
PLALT
PLDIR
PLDIN
PLDOUT
PLWKPU
PLSCHEN
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
FD28
FD2A
FE00
FE02
FE04
FE0A
FE0C
FE0E
FE10
FE40
FE42
FE44
FE46
FE48
FE4A
FE4C
FE4E
FE60
FE62
FE64
FE66
FE68
FE80
FE82
FE84
FE86
FE88
FE8A
FE8C
FE8E
FEE0
FEE2
FEE4
FEE6
FEE8
FEEA
FF00
FF02
FF04
FF06
FF08
FF0A
Read/Write
Read/Write
Read Only
Read Only
Read/Write
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read Only
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Port F Weak Pull-Up Register
Port F Schmitt Trigger Enable Register
Interrupt Vector Register
NMI Status Register
External NMI Control/Status Register
Interrupt Status Register 0
Interrupt Status Register 1
Interrupt and Enable Mask Register 0
Interrupt and Enable Mask Register 1
USART 1 Transmit Data Buffer
USART 1 Receive Data Buffer
USART 1 Interrupt Control Register
USART 1 Status Register
USART 1 Frame Select Register
USART 1 Mode Select Register
USART 1 Baud Rate Divisor Register
USART 1 Baud Rate Prescaler
MICROWIRE Data Register
MICROWIRE Control 1 Register
MICROWIRE Control 2 Register
MICROWIRE Control 3 Register
MICROWIRE Status Register
USART 2 Transmit Data Buffer
USART 2 Receive Data Buffer
USART 2 Interrupt Control Register
USART 2 Status Register
USART 2 Frame Select Register
USART 2 Mode Select Register
USART 2 Baud Rate Divisor Register
USART 2 Baud Rate Prescaler
Port I Alternate Function Register
Port I Direction Register
Port I Data Input Register
Port I Data Output Register
Port I Weak Pull-Up Register
Port I Schmitt Trigger Enable Register
Port L Alternate Function Register
Port L Direction Register
Port L Data Input Register (read-only)
Port L Data Output Register
Port L Weak Pull-Up Register
Port L Schmitt Trigger Enable Register
Table 21
Device Detailed Memory Map
Register Name
Size
Register
Address
(hex)
Access
Type
Contents