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| 型號(hào)： | CR16MES544VE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 50/99頁 |
| 文件大小： | 449K |
| 代理商： | CR16MES544VE |
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14.2.3
Mode 3 is the Dual Independent Timer mode, which gener-
ates system timing signals or counts occurrences of external
events.
Figure15 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 3. The timer is configured to oper-
ate as a dual independent system timer or dual external
Mode 3: Dual Independent Timer/Counter
event counter. In addition, Timer/Counter I can generate a
50% duty cycle PWM signal on the TnA pin. The TnB pin can
be used as an external event input or pulse accumulate input
and can be used as the clock source for either Timer/Counter
I or Timer/Counter II. Both counters can also be clocked by
the prescaled system clock.
Timer/Counter I (TnCNT1) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRA
register and counting proceeds down from the reloaded val-
ue. In addition, the TnA pin is toggled on each underflow if
this function is enabled by the TnAEN bit. The initial state of
the TnA pin is software-programmable. When the TnA pin is
toggled from low to high, it sets the TnCPND interrupt pend-
ing flag and also generates an interrupt if the interrupt is en-
abled by the TnAIEN bit.
Because TnA toggles on every underflow, a 50% duty cycle
PWM signal can be generated on TnA without any further ac-
tion from the CPU once the pulse train is initiated.
Timer/Counter II (TnCNT2) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRB
register and counting proceeds down from the reloaded val-
ue. In addition, each underflow sets the TnDPND interrupt
pending flag and generates an interrupt if the interrupt is en-
abled by the TnDIEN bit.
14.2.4
Mode 4 is the Single Input Capture and Single Timer mode,
which provides one external event counter and one system
timer.
Figure16 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 4. This mode offers a combination
of Mode 3 and Mode 2 functions. Timer/Counter I is used as
a system timer as in Mode 3 and Timer/Counter II is used as
a capture timer as in Mode 2, but with a single input rather
than two inputs.
Timer/Counter I (TnCNT1) operates the same as in Mode 3.
It counts down at the rate of the selected clock. Upon under-
flow, it is reloaded from the TnCRA register and counting pro-
ceeds down from the reloaded value. The TnA pin is toggled
on each underflow if this function is enabled by the TnAEN
bit. When the TnA pin is toggled from low to high, it sets the
TnCPND interrupt pending flag and also generates an inter-
rupt if the interrupt is enabled by the TnAIEN bit. A 50% duty
cycle PWM signal can be generated on TnA without any fur-
ther action from the CPU once the pulse train is initiated.
Mode 4: Input Capture Plus Timer
Figure 15.
Mode 3: Dual Independent Timer/Counter Block Diagram
Reload A
TnCRA
Timer/Counter I
TnCNT1
Reload B
TnCRB
Timer I
Clock
TnA
TnAIEN
TnAPND
TnDIEN
TnDPND
Timer
Interrupt I
Timer
Interrupt II
TnAEN
Timer/Counter II
TnCNT2
Timer II
Clock
TnB
Clock
Selector
Underflow
Underflow
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| CR16MES944VI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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