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15.5.3
The MWCTL2 register is a byte-wide, read/write register that
controls the clock divider used to generate the MSK shift
clock from the system clock. The MICROWIRE interface
module generates the MSK clock only in master mode, so
this register is ignored in slave mode. Upon reset, all non-re-
served bits are cleared to 0. The register format is shown be-
low.
7
6
5
MDV1
MICROWIRE Control 2 Register (MWCTL2)
MCDV
MICROWIRE Clock Divider Value. This 7-bit
field specifies the divide-by factor used for gen-
erating the MSK shift clock from the system
clock. The divide-by factor is 2*(MCDV+1).
This allows selection of a divide-by ratio from 2
to 256. This field is ignored in slave mode
(MWCTL1.MMNS=0) or if the MDV1 bit is set.
MICROWIRE Clock Divide-by-1. When cleared
to 0, the MSK shift clock rate is determined by
the MCDV field. When set to 1, the divide-by
factor is 1 and the MSK clock operates at the
same rate as the system clock. This bit is ig-
nored in slave mode (MWCTL1.MMNS=0).
MDV1
15.5.4
The MWCTL3 register is a byte-wide, read/write register that
controls the MRDY pin and enables or disables the MI-
CROWIRE interrupts and echo back function. Upon reset, all
non-reserved bits are cleared to 0. When the software writes
to this register, the reserved bits must be written with 0 for the
MICROWIRE interface to function properly. The register for-
mat is shown below.
7
6
5
4
Reserved MEIW
MEIR MEIO
MICROWIRE Control 3 Register (MWCTL3)
MBFL
MICROWIRE Buffer Length. This bit sets the
data buffer length in slave mode to either one
or two bytes.
When MBFL is cleared to 0, the buffer length is
one byte. The MRDY pin goes high when trans-
mission or reception of one data byte is com-
pleted. This is the proper setting for slave
mode.
When MBFL is set to 1, the buffer length is two
bytes. The MRDY pin goes high when the read
buffer is full and a subsequent transmission or
reception of a data byte is completed. This set-
ting is only intended for master mode and
should not be used for slave mode.
MICROWIRE Ready. This write-only bit allows
the software to control the MRDY pin when the
device operates in slave mode. Writing a 1 to
this bit position asserts the MRDY pin (makes
it go low). This should be done only when the
MICROWIRE interface is idle (MWSTAT.MB-
SY=0).
The hardware changes the MRDY pin from low
to high at the end of a data transfer, as defined
by the MBFL bit.
Writing a 0 to MRDY has no effect. The MRDY
MRDY
bit is ignored entirely in master mode
(MWCTL1.MMNS=1).
Reading this bit returns an unknown value.
MICROWIRE Echo Back. This bit enables (1)
or disables (0) the echo back function in slave
mode. This bit should be written only when the
MICROWIRE interface is idle (MWSTAT.MB-
SY=0). The MECH bit is ignored in master
mode.
In the echo back mode, MDODI is transmitted
(echoed back) on MDIDO if MWDAT does not
contain any valid data. With the echo back
function disabled, the data held in the MWDAT
register is transmitted on MDIDO, whether or
not the data is valid.
MICROWIRE Enable Interrupt on Overrun.
This bit enables or disables the overrun error
interrupt. When set to 1, an interrupt is gener-
ated when the Receive Overrun Error flag
(MWSTAT.MOVR) is set. Otherwise, no inter-
rupt is generated when an overrun error oc-
curs. This bit should only be enabled in master
mode.
MICROWIRE Enable Interrupt for Read. When
set to 1, an interrupt is generated when the
Read Buffer Full flag (MWSTAT.MRBF) is set.
Otherwise, no interrupt is generated when the
read buffer is full.
MICROWIRE Enable Interrupt for Write. When
set to 1, an interrupt is generated when the
Busy bit (MWSTAT.MBSY) is cleared, which in-
dicates that a data transfer sequence has been
completed and the read buffer is ready to re-
ceive the new data. Otherwise, no interrupt is
generated when the Busy bit is cleared.
MECH
MEIO
MEIR
MEIW
15.5.5
The MICROWIRE Status Register is a byte-wide, read-only
register that shows the current status of the MICROWIRE in-
terface module. Upon reset, all non-reserved bits are cleared
to 0. The register format is shown below.
7
6
5
4
3
Reserved
MOVR
Reserved
MICROWIRE Status Register (MWSTAT)
MBSY
MICROWIRE Busy. This bit, when set to 1, in-
dicates that the MICROWIRE shifter is busy.
In master mode, MBSY is set to 1 when the
MWDAT register is written. In slave mode, this
bit is set to 1 on the first leading edge of MSK
when MCS is asserted or when the MWDAT
register is written, whatever occurs first.
In both master and slave modes, this bit is
cleared to 0 when the MICROWIRE data trans-
fer sequence is completed and the read buffer
is ready to receive the new data; in other
words, when the previous data held in the read
buffer has already been read.
If the previous data in the read buffer has not
been read and a new data has been received
into the shift register, the MBSY will not be
cleared, as the transfer could not be complet-
ed. This is because the contents of the shift
4
3
2
1
0
MCDV
3
2
1
0
MECH
MRDY MBFL
2
1
0
MRBF
MBSY