參數(shù)資料
型號(hào)： CR16MES544VE
廠商： National Semiconductor Corporation
元件分類： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 13/99頁(yè)
文件大?。?/td> 449K
代理商： CR16MES544VE
13
www.national.com
4.0
System Configuration
The CR16MHS9 has two input pins, ENV0 and ENV1, which
are used to specify the operating environment of the device
upon reset. There are also two system configuration regis-
ters, called the Module Configuration (MCFG) register and
the Module Status (MSTAT) register.
4.1
Upon reset, the operating mode of the device is determined
by the state of the ENV0 and ENV1 input pins, as indicated
in Table6.
Table 6
Operating Environment Selection
ENV0 AND ENV1 PINS
In the case where the ENV1 and ENV0 pins are both high,
the reset algorithm looks at the FLCTRL2.EMPTY bit to de-
termine whether the program memory is empty, and sets the
operating mode accordingly.
The ENV0 and ENV1 pins have on-chip pull-up devices that
are enabled during reset while the pins are being sampled.
Therefore, if they are left unconnected, the inputs are consid-
ered high and the normal operating mode (IRE-Mode) is se-
lected and the CPU starts to execute code at address 0. To
enter any other operating mode, the external hardware must
drive the appropriate input low.
In the case where the ISP-Mode is selected, the chip starts
executing the ISP code residing in the on-chip boot ROM ar-
ea.
The Test Modes are reserved for factory testing and for ex-
ternal programming of the flash program memory; they
should not be invoked otherwise.
4.2
MODULE CONFIGURATION (MCFG)
REGISTER
The MCFG register is a byte-wide, read/write register that
sets the general programmable features of the device.
Upon reset, the non-reserved bits of this register are cleared
to zero. The start-up software must write a specific value to
this register in order to configure the CLK output pin function.
When the software writes to this register, it must write a zero
to each reserved bit for the device to operate properly. The
register should be written in active mode only, not in power
save, HALT, or IDLE mode. However, the register contents
are preserved during all power modes.
The MCFG register format is shown below.
CLKOE
CPU Clock Output Enable. When this bit is
cleared (0), the CLK pin remains in the high-im-
pedance state. When this bit is set (1) in normal
operating mode, the CLK pin operates as a
CPU clock output.
Slow Clock Output Enable. When cleared (0),
the SLCLK pin of the 44-pin package (ENV0-44
pin) remains in the high-impedance state.
When set (1), this pin produces the slow clock
as an output.
Fast EEPROM Data Memory Access. This bit
is set (1) for zero-wait-state access to the EE-
PROM data memory, or cleared (0) for one-
wait-state access to the data ROM. For infor-
mation on the required number of wait states,
see Table8.
Slow Clock Output Enable. When cleared (0),
the SLCLK pin of the 80-pin package (ENV0-80
pin) remains in the high-impedance state.
When set (1), this pin produces the slow clock
as an output.
CPU Clock Divide-by-2 Output Enable. When
this bit is cleared (0), the CLKOUT2 pin re-
mains in the high-impedance state. When this
bit is set (1) and the CLKOE bit is cleared, the
CLKOUT2 pin operates as clock output, with a
frequency of one-half that of the CPU clock.
SLCLKOE
FEEDM
SLCOE2
CLK2OE
4.3
MODULE STATUS (MSTAT) REGISTER
The MSTAT register is a byte-wide, read-only register that in-
dicates the general status of the device.
The MCFG register format is shown below.
7
4
3
Reserved
PGMBUSY
Reserved
OENV(1:0)
Operating Environment. These two bits contain
the values applied to the ENV1 and ENV0 pins
upon reset. These bit values are controlled by
the external hardware upon reset and are held
constant in the register until the next reset.
Flash Programming Busy. This bit is automati-
cally set to 1 when either the program memory
or the data memory is busy being programmed.
It is cleared to 0 when neither of the two flash
memories are busy being programmed. When
this bit is set, the software should not attempt
to access either of these two memories.
PGMBUSY
ENV1
ENV0
Operating Environment
0
0
1
0
1
0
Test Mode
Test Mode
In-System Programming mode
Internal ROM enabled Mode (IRE), if
program memory is not empty; or ISP-
Mode, if program memory is empty
1
1
7
6
5
4
3
2
1
0
Reserved
CLK2OE
SLCOE2
FEEDM
SLCLKOE
CLKOE
Reserved
2
1
0
OENV1
OENV0
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