參數(shù)資料
型號(hào)： CR16MES544VE
廠商： National Semiconductor Corporation
元件分類(lèi)： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 30/99頁(yè)
文件大?。?/td> 449K
代理商： CR16MES544VE
www.national.com
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be enabled by setting either of two control bits in the External
NMI Control/Status (EXNMI) register. The two bits are called
the EN (Enable) bit and the ENLCK (Enable and Lock) bit.
The EN bit enables the NMI trap until an NMI trap event or a
reset occurs. An NMI trap automatically resets the EN bit. Us-
ing this bit to enable the NMI trap is intended for applications
where the NMI pin is toggled frequently but nested NMI traps
are not needed. The trap service routine should re-enable the
NMI trap by setting the EN bit before returning to the main
program.
The ENLCK bit enables the NMI trap and locks it in the en-
abled state. In other words, it leaves the NMI trap enabled
even after the trap occurs. It can be cleared only by a reset
operation. After the bit is set, an NMI trap is triggered by each
falling edge on the NMI pin, allowing nested NMI traps.
To use the EN bit, the ENLCK must remain cleared to 0. Oth-
erwise, the EN bit is ignored.
9.3
MASKABLE INTERRUPTS
Maskable interrupts can be enabled or disabled under soft-
ware control. There are 16 maskable interrupt sources (in-
cluding some reserved for future expansion), organized into
levels of priority. If more than one interrupt event occurs at
any given time, the interrupt source with the highest priority
is serviced first. The others must wait until the highest-priority
interrupt is serviced and is no longer pending.
Figure11 lists the maskable interrupt sources of the device
in order of priority, from the highest-priority interrupt (IRQ15)
to the lowest (IRQ0).
Table 11
Maskable Interrupt Priority List
To enable a maskable interrupt, the enable bit must be set in
the applicable peripheral module and also in the appropriate
Interrupt and Enable Mask register, IENAM0 or IENAM1. In
addition, both the Global Maskable Interrupt Enable bit (I)
and the Local Maskable Interrupt Enable bit (E) must be set
to 1 in the PSR register. If either one of these bits is 0, then
all maskable interrupts are disabled.
Both the E bit and I bit can be controlled with the Load Pro-
cessor Register (LPR) instruction. In addition, the E bit is
easily changed by executing the Enable Interrupts (EI) or
Disable Interrupts (DI) instruction. Using the EI and DI in-
structions avoids the possibility of an interrupt occurring with-
in a read-modify-write operation on the PSR register.
For more information on the PSR bits, see Section6.3.
9.4
The Interrupt Control Unit uses the following interrupt control
and status registers:
Non-Maskable Interrupt Status Register (NMISTAT)
External NMI Control/Status Register (EXNMI)
Interrupt Enable and Mask Register 0 (IENAM0)
Interrupt Enable and Mask Register 1 (IENAM1)
Interrupt Vector Register (IVCT)
Interrupt Status Register 0 (ISTAT0)
Interrupt Status Register 1 (ISTAT1)
The following CPU core registers are also used in processing
interrupts:
Interrupt Stack Pointer (ISP)
Interrupt Base Register (INTBASE)
Processor Status Register (PSR)
INTERRUPT REGISTERS
Interrupt Request
Source
IRQ15
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
Reserved (highest priority)
Timer 0
Timer 1 Input A
Timer 1 Input B
Timer 2 Input A
Timer 2 Input B
USART1 Rx
USART2 Rx
Reserved
MICROWIRE/SPI Rx/Tx
USART1 Tx
USART2 Tx
Reserved
Multi-Input Wake-Up
A/D Converter
Reserved (lowest priority)
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