參數(shù)資料
型號： CR16MES544VE
廠商： National Semiconductor Corporation
元件分類： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁數(shù)： 20/99頁
文件大小： 449K
代理商： CR16MES544VE
www.national.com
20
bus width may have to be set to 8 bits depend-
ing on the requirements of the external hard-
ware.
Post Idle
An idle cycle follows the current bus cycle,
when the next bus cycle is in a different zone.
For the 80-pin package where all zones are on-
chip, this bit can be cleared to 0; as this addi-
tional idle-cycle is not required.
IPST
7.2.3
The Static Zone 0 Configuration (SZCFG0) register is a
word-wide, read/write register that sets the timing and bus
characteristics of Zone 0 memory accesses. In the
CR16MHS9 implementation of the CompactRISC architec-
ture, Zone 0 is occupied by the flash EEPROM program
memory.
The SZCFG0 register address is F904 hex. Upon reset, the
register is initialized to 069F hex. The register format is
shown below.
15
14
13
12
11
Reserved
FRE
IPRE
Static Zone 0 Configuration (SZCFG0) Register
WAIT
Memory Wait cycles
This field specifies the number of TIW (internal
wait state) clock cycles added for each memory
access, ranging from 000 binary for no addi-
tional TIW wait cycles to 111 binary for seven
additional TIW wait cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
Memory Hold cycles
This field specifies the number of Thold clock
cycles used for each memory access, ranging
from 00 binary for no Thold cycles to 11 binary
for three Thold clock cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
BW defines the external bus width for the zone.
Bus width is initialized during reset to its default
value, which is 16 bits. If this bit is cleared to 0
the external bus is 8 bits wide. To set to exter-
nal bus width to 16 bits, this bit has to be set to
1. For the 80 pin package the Bus width has to
be set to 1.
Post Idle
An idle cycle follows the current bus cycle,
when the next bus cycle is in a different zone.
For the 80-pin package where all zones are on-
chip, this bit can be cleared to 0 as this addi-
tional idle-cycle is not required.
Preliminary Idle
An idle cycle is inserted prior to the current bus
cycle, when this bus cycle is in a new zone. For
the 80-pin package where all zones are on-
chip, this bit can be cleared to 0 as this addi-
tional idle-cycle is not required.
Fast Read Enable
This bit enables (1) or disables (0) fast read bus
cycles. A fast read operation takes one clock
HOLD
BW
IPST
IPRE
FRE
cycle. A normal read operation takes at least
two clock cycles.
Note 1:
These bits (bit 5 and 6) control the configuration to
the 224-pin device used in emulation equipment. The CPU
should clear these bits to 0 when it writes to the register.
7.3
The number of wait cycles and hold cycles inserted into a bus
cycle depends on whether it is a read or write operation, the
type of memory or I/O being accessed, and the control regis-
ter settings.
WAIT AND HOLD STATES USED
7.3.1
When the CPU accesses the flash program memory (ad-
dress 0000-BFFF hex), the number of added wait and hold
cycles depends on type of accesses and the BIU register set-
tings.
For a read operation in fast read mode (SZCFG0.FRE=1), no
wait cycles or hold cycles are used.
For a read operation in normal read mode (SZCFG0.FRE=0),
the number of inserted wait cycles is one plus the value writ-
ten to the SZCFG0.WAIT field. The number in this field can
range from zero to seven, so the total number of wait cycles
can range from one to eight. The number of inserted hold cy-
cles is equal to the value written to the SCCFG0.HOLD field,
which can range from zero to three.
For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is one. No hold cycles are
used.
For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0. WAIT field plus one (in the late write mode) or two
(in the early write mode). The number of inserted hold cycles
is equal to the value written to the SCCFG0.HOLD field,
which can range from zero to three.
Writing to the flash program memory is a ROM programming
operation that requires some additional steps, as explained
in Section8.3.2.
Flash Program Memory
7.3.2
When the CPU accesses RAM memory (address E000-
E7FF hex), no wait cycles or hold cycles are used.
RAM Memory
7.3.3
There is either no wait state or one wait state used when the
CPU accesses the EEPROM data memory (address F000-
F27F hex). The number of required wait states (zero or one)
depends on the CPU clock frequency and operating mode,
and is controlled by programming of the FEEDM bit in the
MCFG register, as explained in Section8.3. No hold cycles
are used.
EEPROM Data Memory
7.3.4
When the CPU accesses core registers and on-chip periph-
erals in the range of F000-FFFF, one wait cycle is used. No
hold cycles are used.
For the FB00-FBFF (Ports B and C) the IOCFG register de-
termines the timing.
Core Register and Peripheral Accesses
10
9
8
IPST
Reserved
7
6
5
4
3
2
1
0
BW
Note 1
HOLD
WAIT
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