參數(shù)資料
型號(hào)： CR16MES544VE
廠商： National Semiconductor Corporation
元件分類： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 56/99頁(yè)
文件大?。?/td> 449K
代理商： CR16MES544VE
www.national.com
56
read buffer has been read. In master mode, an Overrun error
occurs when the read buffer is full, the 8-bit shifter is full and
a new data transfer sequence starts.
The “Receive Buffer Full” (MRBF) bit indicates if the MWDAT
register holds valid data. The MOVR bit indicates that an
overrun condition has occurred.
15.1.3
The “MICROWIRE Busy” (MBSY) bit indicates whether the
MWDAT register can be written. All write operations to the
MWDAT register update the shifter while the data contained in
the read buffer is not affected. Undefined results will occur if
the MWDAT register is written while the MBSY bit is set to 1.
Writing
15.1.4
Two clocking modes are supported: the normal mode and the
alternate mode.
In the normal mode, the output data is shifted out on the ris-
ing edge of MSK on the MDODI pin (master mode) or MDIDO
(slave mode). The input data, which is received via MDIDO
pin (master mode) or the MDODI pin (slave mode), is sam-
pled on the fallowing edge of MSK.
In the alternate mode, the output data is shifted out on the ris-
ing edge of MSK on the MDODI pin (master mode) or MDIDO
pin (slave mode). The input data, which is received via MDI-
DO pin (master mode) or MDODI pin (slave mode), is sam-
pled on the falling edge of MSK.
Clocking Modes
The clocking modes are selected with the MSKM bit. The
MIDL bit allows selection of the value of MSK when it is idle
(when there is no data being transferred). Various MSK clock
frequencies can be programmed via the MCDV bits. Figures
19, 20, 21, and 22 show the data transfer timing for the nor-
mal and the alternate modes with the MIDL bit equal to 0 and
equal to 1.
Note that when data is shifted out on MDODI (master mode)
or MDIDO (slave mode) on the leading edge of the MSK
clock, bit 6 is shifted out on the second leading edge of the
MSK clock. When data are shifted out on MDODI (master
mode) or MDIDO (slave mode) on the trailing edge of MSK,
bit 6 is shifted out on the first trailing edge of MSK.
15.2
MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the 8-bit shifter (MWDAT regis-
ter), eight clocks are generated to shift the eight bits of data
and then MSK goes idle again. The MSK idle state can be ei-
ther high or low, depending on the MIDL bit.
If MDIDO is sampled on the leading edge of MSK, a se-
quence of eight clock is generated after a delay that may
range from half a period of MSK to one and a half periods of
MSK. If MDIDO is sampled on the trailing edge of MSK, a se-
Figure 18.
MICROWIRE Block Diagram
Master
Master
Slave
Slave
8-bit Shift Register
Master
Clock Prescaler + Select
8
Read Buffer
MWDAT
System Clock
Write Data
Read Data
Control + Status
Interrupt Request
Data In
Data Out
MSK
MCS
MRDY
MDODI
MDIDO
MSK
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CR16MES944VE 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers
CR16MES944VI 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers
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