參數(shù)資料
型號: CR16MES544VE
廠商: National Semiconductor Corporation
元件分類: 16位微控制器
英文描述: Family of CompactRISC 16-Bit Microcontrollers
中文描述: 家庭CompactRISC 16位微控制器
文件頁數(shù): 58/99頁
文件大小: 449K
代理商: CR16MES544VE
www.national.com
58
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the “Echo
Enable” (MECH) bit is set to 1, the data received from MDO-
DI is transmitted on MDIDO in addition to being shifted to
MWDAT. If the MECH bit is cleared to 0, the data transmitted
on MDIDO is the data held in the MWDAT register, regard-
less of its validity. The master may negate the MCS signal to
synchronize the bit count between the master and the slave.
In the case that the slave is the only slave in the system, MCS
can be tied to V
SS
.
An additional output signal, MRDY may be used. This signal
supports very low-end slaves by indicating to the master the
current status of the MICROWIRE channel.
Upon reset, MRDY is inactive. Before transfer starts, MRDY
should be asserted by setting the MWCTL3.MRDY bit.
MRDY is de-asserted when the data transfer of one data byte
has been completed.
MRDY is asserted again only by writing 1 to the MRDY bit.
This should be done after the MWDAT register is read.
15.4
An interrupt is generated in any of the following cases:
When the read buffer is full (MRBF=1) and the “Enable In-
terrupt for Read” bit is set (MEIR=1).
Whenever the shifter is not busy, i.e. the MBSY bit is
cleared (MBSY=0) and the “Enable Interrupt for Write” bit
is set (MEIW=1).
INTERRUPT GENERATION
When an overrun condition occurs (MOVR is set to 1) and
the “Enable Interrupt on Overrun” bit is set (MEIO=1). This
usage is restricted to master mode.
Figure24 illustrates the various interrupt capabilities of this
module.
Figure 22.
Alternate Mode, MIDL Bit = 1
End of Transfer
Sample Point
Shift Out
Data Out
Data In
msb
msb-1
msb-2
Bit 1
Bit 0 (lsb)
msb
msb-1
msb-2
Bit 1
Bit 0 (lsb)
MSKn
Figure 23.
Slave, Normal Mode, MIDL Bit = 0, MRBF Bit = 1
MSK
Sample Point
(MSB)
Bit 7 In
(MSB)
Bit 7 Out
Bit 6
Bit 5
Bit 1
Bit 0
Bit 6
Bit 5
Bit 1
Bit 0
End of Transfer
Shift Out
READY Bit
Set to 1
MDIDO
MDODI
MCS
MRDY
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