參數(shù)資料
型號(hào)： CR16MES544VE
廠商： National Semiconductor Corporation
元件分類： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 71/99頁(yè)
文件大?。?/td> 449K
代理商： CR16MES544VE
71
www.national.com
18.0 A/D Converter
The A/D Converter (ADC) module is an 8-channel, multi-
plexed-input, analog-to-digital converter. The A/D Converter
receives an analog voltage on an input pin and converts that
voltage into an 8-bit digital value using successive approxi-
mation. The CPU can then read the result from a memory-
mapped register. The module supports four automated oper-
ating modes, providing single-channel or 4-channel scanned
operation in single-conversion or continuous mode.
Figure34 is a block diagram of the A/D Converter module.
The analog input signal is selected from eight analog inputs
using an 8-channel analog multiplexer. The input pins are al-
ternate functions of Port I.
A sample-and-hold circuit samples the analog voltage prior
to conversion and holds it stable and throughout the conver-
sion process. A programmable initial delay period allows the
sampled voltage to stabilize before the conversion process
begins.
A capacitor should be connected between the V
REF
and the
AV
CC
pin in order to minimize noise. The recommended val-
ue for this capacitor is about 0.47
μ
F
The input voltage range is from 0V to V
REF
(the A/D refer-
ence voltage). The 80-pin device have a separate pin, V
REF
,
for the reference voltage. The 44-pin devices use the AV
CC
(analog V
CC
) power supply pin as the reference voltage.
The internal analog-to-digital converter block is based on a
successive approximation algorithm, which compares the
sampled voltage against an internally generated sequence of
analog voltages. The result is a linear conversion of the ana-
log voltage to an unsigned 8-bit value ranging from 00 hex for
0.0 volts to FF hex for VREF.
The clock used by the converter block is generated by a clock
divider that scales down the system clock by a programma-
ble factor. The conversion algorithm requires ten A/D Con-
verter clock cycles, or 10 microseconds at the maximum
allowed A/D Converter clock rate of 1 MHz.
Conversion can start after the power supply is stable and AD-
CEN set for 100
μ
s.
The conversion results are stored in a 4-level data buffer. De-
pending on the operating mode, the buffer can hold the re-
sults of four successive conversions from a single channel or
four conversions from adjacent channels scanned in se-
quence.
18.1
The A/D Converter can be configured to operate in any one
of four modes:
Single channel, single conversion
Single channel, continuous conversion
4-channel scan, single conversion
4-channel scan, continuous conversion
The configuration is set by the SCAN and CONT fields in the
ADC Control 2 Register (ADCCNT2), as indicated in
Table19. The A/D converter must be disabled when switch-
ing to a different mode.
Table 19
ADC Operation Modes
OPERATING MODES
18.1.1
In the single channel, single conversion mode, the A/D Con-
verter performs a single conversion using a specified chan-
nel.
The software starts a conversion by setting the START bit in
the ADCCNT2 register. Upon completion of the conversion,
the A/D Converter places the result in register ADDATA0,
clears the START bit, and sets the EOC (end of conversion)
bit in the ADCST register. If the A/D Converter interrupt is en-
abled, an interrupt to the CPU is generated at this time.
Single Channel, Single Conversion Mode
SCAN CONT
Mode
00
00
01
01
0
1
0
1
Single Channel, Single Conversion
Single Channel, Continuous Conversion
4 Channels Scan, Single Conversion
4 Channel Scan, Continuous Conversion
Figure 34.
A/D Converter Block Diagram
SAMPLE
&
HOLD
CONFIGURATION
STATUS
&
CONTROL
DATA
BUFFER
CLOCK
DIVIDER
PERIPHERAL
BUS
CLK
CLK
V
REF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ANALOG
TO
DIGITAL
CONVERTER
/
/
3
5
8:1
ANALOG
MUX
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