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| 型號： | CR16MES544VE |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | Family of CompactRISC 16-Bit Microcontrollers |
| 中文描述： | 家庭CompactRISC 16位微控制器 |
| 文件頁數(shù)： | 53/99頁 |
| 文件大?。?/td> | 449K |
| 代理商： | CR16MES544VE |
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011 = pulse accumulate mode based on TnB
(modes 1 and 3 only)
100 = slow clock *
other values = undefined
Counter II Clock Select. This 3-bit field defines
the clock mode for Timer/Counter II as follows:
C2CSEL
000 = no clock (Timer/Counter II stopped
modes 1, 2, and 3 only)
001 = prescaled system clock
010 = external event on TnB (modes 1 and 3
only)
011 = pulse accumulate mode based on TnB
(modes 1 and 3 only)
100 = slow clock *
other values = undefined
* Operation of the slow clock is determined by the CRC-
TRL.SCLK control bit, as described in Section11.6.1.
14.5.3
The Timer/Counter I (TnCNT1) register is a word-wide, read/
write register that holds the current count value for Timer/
Counter I. The register contents are not affected by a reset
and are unknown upon power-up.
Timer/Counter I Register (TnCNT1)
14.5.4
The Timer/Counter II (TnCNT2) register is a word-wide, read/
write register that holds the current count value for Timer/
Counter II. The register contents are not affected by a reset
and are unknown upon power-up.
Timer/Counter II Register (TnCNT2)
14.5.5
The Reload/Capture A (TnCRA) register is a word-wide,
read/write register that holds the reload or capture value for
Timer/Counter I. The register contents are not affected by a
reset and are unknown upon power-up.
Reload/Capture A Register (TnCRA)
14.5.6
The Reload/Capture B (TnCRB) register is a word-wide,
read/write register that holds the reload or capture value for
Timer/Counter II. The register contents are not affected by a
reset and are unknown upon power-up.
Reload/Capture B Register (TnCRB)
14.5.7
The Timer Mode Control (TnCTRL) register is a byte-wide,
read/write register that sets the operating mode of the timer/
counter and the TnA and TnB pins. This register is cleared
upon reset. The register format is shown below.
Timer Mode Control Register (TnCTRL)
MDSEL
Mode Select. This 2-bit field sets the operating
mode of the timer/counter as follows:
00 = Mode 1: PWM plus system timer
01 = Mode 2: Dual Input Capture plus system
timer
10 = Mode 3: Dual Timer/Counter
11 = Mode 4: Single Input Capture and Single
Timer
TnA Edge Polarity. When cleared (0), input pin
TnA is sensitive to falling edges (high to low
TnAEDG
transitions). When set (1), input pin TnA is sen-
sitive to rising edges (low to high transitions).
TnB Edge Polarity. When cleared (0), input pin
TnB is sensitive to falling edges (high to low
transitions). When set (1), input pin TnB is sen-
sitive to rising edges (low to high transitions). In
pulse accumulate mode, when this bit is set (1),
the counter is enabled only when TnB is high;
when this bit is cleared (0), the counter is en-
abled only when TnB is low.
TnA Enable. When set (1), the TnA pin is en-
abled to operate as a preset input or as a PWM
output, depending on the timer operating
mode. In Mode 2 (Dual Input Capture), a tran-
sition on the TnA pin presets the TnCNT1
counter to FFFF hex. In the other modes, TnA
functions as a PWM output. When this bit is
cleared (0), operation of the pin for the timer/
counter is disabled.
TnB Enable. When set (1), the TnB pin in en-
abled to operate in Mode 2 (Dual Input Cap-
ture) or Mode 4 (Single Input Capture and
Single Timer). A transition on the TnB pin pre-
sets the corresponding timer/counter to FFFF
hex (TnCNT1 in Mode 2 or TnCNT2 in Mode
4). When this bit is cleared (0), operation of the
pin for the timer/counter is disabled. This bit
setting has no effect in Mode 1 or Mode 3.
TnA Output Data. This is a status bit that indi-
cates the current state of the TnA pin when the
pin is used as a PWM output. When set (1), the
TnA pin is high; when cleared (0), the TnA pin
is low. The hardware sets and clears this bit,
but the software can also read or write this bit
at any time and thus control the state of the out-
put pin. In case of conflict, a software write has
precedence over a hardware update. This bit
setting has no effect when TnA is used as an
input.
TnBEDG
TnAEN
TnBEN
TnAOUT
14.5.8
The Timer Interrupt Control (TnICTL) register is a byte-wide,
read/write register that contains the interrupt enable bits and
interrupt pending bits for the four timer interrupt sources,
designated A, B, C, and D. The condition that causes each
type of interrupt depends on the operating mode, as shown
in Table15.
This register is cleared upon reset. The register format is
shown below.
Timer Interrupt Control Register (TnICTL)
TnAPND
Timer Interrupt Source A Pending. When this
bit is set (1), it indicates that timer interrupt con-
dition “A” has occurred. When this bit is cleared
(0), it indicates that the interrupt condition has
not occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table15
This bit can be set by the hardware or by the
software. To clear this bit, the software must
use the Timer Interrupt Clear Register (TnI-
7
6
5
4
3
2
1
0
Reserved
TnAOUT
TnBEN
TnAEN
TnBEDG
TnAEDG
MDSEL
7
6
5
4
3
2
1
0
TnDIEN
TnCIEN
TnBIEN
TnAIEN
TnDPND
TnCPND TnBPND TnAPND
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| CR16MES544VI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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| CR16MES944VI | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of CompactRISC 16-Bit Microcontrollers |
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