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off during power-save operation, thus reducing power con-
sumption and radiated emissions. This can be done only if
the module detects a toggling low-speed oscillator. If the low-
speed oscillator is not operating, the prescaler remains avail-
able as the slow clock source.
11.4
POWER-ON RESET
The Power-On Reset circuit generates a system reset signal
upon power-up and holds the signal active for a period of
time to allow the crystal oscillator to stabilize. The circuit de-
tects a power turn-on condition, which presets the 14-bit tim-
er to 3FFF hex. Once oscillation starts and the clock
becomes active, the timer starts counting down. When the
count reaches zero, the 14-bit timer stops counting and the
internal reset signal is deactivated (unless the RESET pin is
held low).
The circuit sets a power-on reset flag bit upon detection of a
power-on condition. The CPU can read this flag to determine
whether a reset was caused by a power-up or by the RESET
input.
Note:
Power-On Reset circuit cannot be used to detect a
drop in the supply voltage.
11.5
EXTERNAL RESET
An active-low reset input pin called RESET allows the device
to be reset at any time. When the signal goes low, it gener-
ates an internal system reset signal that remains active until
the RESET signal goes high again.
11.6
DUAL CLOCK AND RESET REGISTERS
The Dual Clock and Reset module (CLK2RES) contains two
registers: the Clock and Reset Control register (CRCTRL)
and the Slow Clock Prescaler register (PRSSC).
11.6.1
Clock and Reset Control Register (CRCTRL) is a byte-wide
read/write register that contains the power-on reset flag and
selects the type of slow clock. The register format is shown
below.
7
6
5
4
Reserved
Clock and Reset Control Register (CRCTRL)
SCLK
Slow Clock Select. When this bit is set to 1, the
32.728 kHz oscillator is used for the slow clock.
When this bit is cleared to 0, the prescaled
main clock is used for the slow clock. Upon re-
set, this bit is cleared to 0.
Power-On Reset. This bit is set to 1 by the
hardware when a power-on condition is detect-
ed, allowing the CPU to determine whether a
power-up has occurred. The CPU can clear
this bit to 0 but cannot set it to 1. Any attempt
by the CPU to set this bit is ignored.
POR
11.7
SLOW CLOCK PRESCALER REGISTER
(PRSSC)
The Slow Clock Prescaler (PRSSC) register is a byte-wide
read/write register that holds the clock divisor used to gener-
ate the slow clock from the main clock. The format of the reg-
ister is shown below.
7
6
5
4
SCDIV
SCDIV
Slow Clock Divisor. If the clock divider is en-
abled (CRCTRL.SCLK=0), the main clock is di-
vided by (SCDIV+1)*2 to produce the slow
system clock. Upon reset, PRSSC register is
set to FF hex.
3
2
1
0
POR
SCLK
3
2
1
0