參數(shù)資料
型號(hào)： CR16MES544VE
廠商： National Semiconductor Corporation
元件分類(lèi)： 16位微控制器
英文描述： Family of CompactRISC 16-Bit Microcontrollers
中文描述： 家庭CompactRISC 16位微控制器
文件頁(yè)數(shù)： 32/99頁(yè)
文件大?。?/td> 449K
代理商： CR16MES544VE
www.national.com
32
9.4.7
The ISTAT1 register is a byte-wide, read-only register that in-
dicates which maskable interrupt inputs to the ICU (IRQ8
through IRQ15) are currently active. The register format is
shown below.
7
6
5
4
IST15 IST14 IST13 IST12 IST11 IST10 IST9
Interrupt Status Register 1 (ISTAT1)
IST(8-15)
Interrupt Status bits. Each bit indicates the cur-
rent status of an interrupt input to the ICU, cor-
responding to interrupts IRQ8 through IRQ15.
A bit set to 1 indicates an active interrupt input,
even when the interrupt is masked out by the
IENAM0 register. A bit cleared to 0 indicates an
inactive interrupt input.
9.4.8
Some of the CPU core registers are used for controlling inter-
rupts: the Processor Status Register (PSR), the Interrupt
Base Register (INTBASE), and the Interrupt Stack Pointer
(ISP) register.
Core Registers (PSR, INTBASE, and ISP)
PSR Register
The Processor Status Register (PSR) is a 16-bit register that
holds status information and selects the operating modes for
the CPU core. Bit 9 and Bit 11 are the Local Maskable Inter-
rupt Enable (E) bit and the Global Maskable Interrupt Enable
(I) bit, respectively, as shown in Figure4. These bits are used
to enable or disable maskable interrupts.
15 14 13 12 11 10 9
8
Reserved
I
P
E
0
Both the E bit and I bit can be controlled with the Load Pro-
cessor Register (LPR) instruction. The E bit can also be con-
trolled by the Enable Interrupts (EI) and Disable Interrupts
(DI) instructions. If the E and I bits are both set to 1, all
maskable interrupts are accepted. Otherwise, only the non-
maskable interrupt is accepted.
Upon reset, the E bit is set to 1 and the I bit is cleared to 0.
The processor uses the I bit to block maskable interrupts
while executing an interrupt handler. When an interrupt oc-
curs, the processor saves the existing I bit (as part of the
PSR) on the interrupt stack and then clears the current I bit
to prevent further interrupts. When RETX is executed, the
former I bit it restored (with the rest of the PSR), again en-
abling masked interrupts.
The E bit is intended to be used in a localized manner, allow-
ing a process to operate without interruption for a short peri-
od while it accesses and modifies system variables and
semaphores. The E bit can be set to 1 by executing the En-
able Interrupt (EI) or cleared to 0 by executing the Disable In-
terrupts (DI) instruction. Using these two instructions avoids
the possibility of an interrupt occurring within a read-modify-
write operation on the PSR register.
INTBASE Register
The Interrupt Base Register (INTBASE) is a 21-bit register
that holds the address of the Dispatch Table for interrupts
and traps. The five most significant bits and the least signifi-
cant bit of this register are always zero. The Dispatch Table
is 32 words long, and limited to the flash program memory
space. Thus, the Dispatch Table must start at an even ad-
dress in the range of 0004 to BFC0 hex.
ISP Register
The Interrupt Stack Pointer (ISP) is a 21-bit register that
points to the lowest address of the last item stored on the in-
terrupt stack. The on-chip hardware modifies the stack con-
tents and stack pointer when an interrupt or trap event occurs
and upon completion of an interrupt or trap service routine.
The five most significant bits and the least significant bit of
this register are always zero. Because the stack must reside
in RAM and the device RAM occupies the address range of
E000-E7FF hex, the interrupt stack is restricted to this range.
9.5
INTERRUPT PROGRAMMING
PROCEDURES
The following subsections provide information on initializing
the device for interrupts, clearing interrupts, and nesting in-
terrupts.
9.5.1
Upon reset, all interrupts are disabled. To program the device
for interrupt operation and to enable interrupts, use the fol-
lowing procedure in the application software:
1. Set the interrupt stack pointer (ISP).
2. Load the INTBASE register so that it points to the base
of the interrupt Dispatch Table in ROM.
3. Perform any required preparation steps for the interrupt
service routines.
4. Initialize the peripheral devices that can generate inter-
rupts and set their respective interrupt enable bits.
5. Use the Load Processor Register (LPR) instruction to
set I bit in the PSR register.
6. When the device is ready to execute interrupts, set the
E bit in the PSR register by executing the Enable Inter-
rupts (EI) instruction.
Once maskable interrupts are enabled by setting the E and I
bits, you can disable and re-enable all maskable interrupts by
using the Enable Interrupts (EI) and Disable Interrupts (DI)
instructions, which set and clear the E bit.
Initialization
9.5.2
Clearing an interrupt request before it is serviced may cause
a spurious interrupt because the CPU may detect an interrupt
not reflected in the Interrupt Vector (IVCT) register. To ensure
reliable operation, clear interrupt requests only while inter-
rupts are disabled.
Changing the polarity of an interrupt input (for example, in the
Multi-Input Wake-Up module) can cause a spurious interrupt,
and therefore should be done only while interrupts are dis-
abled.
For the same reason, clearing an enable bit in a peripheral
module should be carried out only while the interrupt is dis-
abled.
Clearing Interrupts
9.5.3
Interrupts may be nested, or in other words, an interrupt ser-
vice routine can itself be interrupted by a different interrupt
source. There is no hardware limitation on the number of in-
Nesting Interrupts
3
2
1
0
IST8
7
N
6
Z
5
F
4
0
3
0
2
L
1
T
0
C
Figure 4.
Processor Status Register (PSR) Format
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