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The crystal oscillator you choose may require external com-
ponents different from the ones specified above. In that case,
consult with National Semiconductor for the component
specifications.
The crystals and other oscillator components should be
placed close to the X1CKI/X1CKO and X2CKI/X2CKO de-
vice input pins to keep the printed trace lengths to an abso-
lute minimum.
Choose capacitor component values in the tables to obtain
the specified load capacitance for the crystal when combined
with the parasitic capacitance of the trace, socket, and pack-
age (which can vary from 0 to 8 pF). As a guideline, the load
capacitance is:
CL = (C1 * C2)/(C1+C2) + Cparasitic
C2 > C1
C1 can be trimmed to obtain the desired load capacitance.
The start-up time of the 32.768 kHz oscillator can vary from
one to six seconds. The long start-up time is due to the high
“Q” value and high serial resistance of the crystal necessary
to minimize power consumption in Power Save mode.
11.2
The main system clock is generated by the main oscillator. It
can be stopped by the Power Management Module to reduce
power consumption during periods of reduced activity. When
the main clock is restarted, a 14-bit timer generates a “Good
Main Clk” signal after a start-up delay of 32,768 clock cycles.
This signal is an indicator that the main clock oscillator is sta-
ble.
The “Stop Main Osc” signal from the Power Management
Module stops and starts the main oscillator. When this signal
MAIN SYSTEM CLOCK
is asserted, it presets the 14-bit timer to 3FFF hex and stops
the main oscillator. When the signal goes inactive, the main
oscillator starts and the 14-bit timer counts down from its pre-
set value. When the timer reaches zero, it stops counting and
asserts the “Good Main Clk” signal.
11.3
The slow (32.768 kHz) clock is necessary for operating the
device in Power Save modes and to provide a clock source
for modules such as the Timing and Watchdog Module.
The slow clock operates in a manner similar to the main
clock. The “Stop Slow Osc” signal from the Power Manage-
ment Module stops and starts the slow oscillator. When this
signal is asserted, it presets a 6-bit timer to 3F hex and dis-
ables the slow oscillator. When the signal goes inactive, the
slow oscillator starts and the 6-bit timer counts down from its
preset value. When the timer reaches zero, it stops counting
and asserts the “Good Low Speed Clk” signal, thus indicating
that the slow clock is stable.
For systems that do not require a reduced power consump-
tion mode, the external crystal network may be omitted for
the slow clock. In that case, the slow clock can be created by
dividing the main clock by a prescaler factor. The prescaler
circuit consists of a fixed divide-by-2 counter and a program-
mable 8-bit prescaler register. This allows a choice of clock
divisors ranging from 2 to 512. The resulting slow clock fre-
quency must not exceed 100 KHz.
A software-programmable multiplexer selects either the
prescaled main clock or the 32.768 kHz oscillator as the slow
clock. Upon reset, the prescaled main clock is selected, en-
suring that the slow clock is always present initially. Selection
of the 32.768 kHz oscillator as the slow clock disables the
clock prescaler, which allows the CLK1 oscillator to be turned
SLOW SYSTEM CLOCK
Table 13
Component Values of the High Frequency Crystal Circuit
Component
Parameters
Values
Values
Values
Values
Tolerance
Oscillator
Resonance Frequency
Type
Max. Serial Resistance
Max. Shunt Capacitance
Load Capacitance
Resistor R1
Resistor R2
Capacitor C1, C2
4 MHz
AT-Cut
75
4 pF
12 pF
1 M
0
22 pF
12 MHz
AT-Cut
35
4 pF
15 pF
1 M
0
20 pF
16 MHz
AT-Cut
35
4 pF
15 pF
1 M
0
20 pF
20 MHz
AT-Cut
35
4 pF
20 pF
1 M
0
20 pF
N/A
Crystal
5%
5%
20%
Table 14
Component Values of the Low Frequency Crystal Circuit
Component
Parameters
Values
Tolerance
Oscillator
Resonance Frequency
Type
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
Resistor R1
Resistor R2
Capacitor C1, C2
32.768kHz
Parallel
N-Cut or XY-bar
40 k
2 pF
9-13 pF
10-20 M
4.7 k
20 pF
N/A
Crystal
5%
5%
20%