參數(shù)資料
型號: C5NPD0-DS
英文描述: QUAD BILATERAL SWITCH FOR TRANSMISSION OR MULTIPLEXING OF ANALOG OR DIGITAL SIGNALS
中文描述: 的C - 5網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂D0
文件頁數(shù): 75/100頁
文件大?。?/td> 2163K
代理商: C5NPD0-DS
AC Timing Specifications
75
MOTOROLA GENERAL BUSINESS INFORMATION
C5NPD0-DS/D REV 04
Gigabit TBI Interface Timing Description
OC-12 Timing Description
DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in
Figure 13
and described in
Table 40
.
Figure 13
DS1/DS3 Ethernet Timing Diagram
10/100 Ethernet Timing Specifications
The 10/100 Ethernet interface timing is shown in
Figure 14
and described in
Table 41
.
CPn_0 (TCLK)
Cycle 1
Cycle 2
Cycle 2
Cycle 3
Cycle 3
Cycle 4
Cycle 4
Cycle 5
Cycle 5
CPn_2/3 (Tx)
CPn_1 (RCLK)
CPn_4/5 (Rx)
T
cdt
T
cdo
T
cdr
T
cds
T
cdh
Table 40
DS1/DS3 Ethernet Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tcdt
DS1/DS3 Transmit Cycle Time
647/22.4
ns
Tcdo
DS1/DS3 Output Time
3.0/3.0
400/15.0
ns
Tcdr
DS1/DS3 Receive Cycle Time
647/22.4
ns
Tcds
DS1/DS3 Setup Time
2.0
ns
Tcdh
DS1/DS3 Hold Time
2.5
ns
F
n
.
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